发明授权
- 专利标题： Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation
- 专利标题（中）： 数字信号处理器计算核心，具有存储器访问级的管线和用于有效操作的多个累积级
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申请号： US09570213申请日： 2000-05-12
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公开(公告)号： US06859872B1公开(公告)日： 2005-02-22
- 发明人: William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman
- 申请人： William C. Anderson , John Edmondson , Jose Fridman , Marc Hoffman
- 申请人地址： US MA Norwood
- 专利权人： Analog Devices, Inc.
- 当前专利权人： Analog Devices, Inc.
- 当前专利权人地址： US MA Norwood
- 代理机构： Wolf, Greenfield & Sacks, P.C.
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06F9/302 ; G06F9/38
摘要：
A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
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