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1.发明授权Digital signal processor computation core with input operand selection from operand bus for dual operations 有权数字信号处理器计算核心，具有来自操作数总线的输入操作数选择，用于双操作公开(公告)号：US07111155B1
公开(公告)日：2006-09-19
申请号：US09570108
申请日：2000-05-12
IPC分类号： G06F7/38
CPC分类号： G06F9/3867 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/30149 , G06F9/3824 , G06F9/3885
摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
摘要翻译： 计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。 计算块包括寄存器文件和双执行单元。 执行单元包括用于在执行数字信号计算时增强性能的特征。 计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。 有限脉冲响应滤波算法在双执行单元上实现了高性能。
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2.发明授权Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation 有权数字信号处理器计算核心，具有存储器访问级的管线和用于有效操作的多个累积级公开(公告)号：US06859872B1
公开(公告)日：2005-02-22
申请号：US09570213
申请日：2000-05-12
CPC分类号： G06F9/3867 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/381 , G06F9/3824 , G06F9/3826
摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
摘要翻译： 计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。 计算块包括寄存器文件和双执行单元。 执行单元包括用于在执行数字信号计算时增强性能的特征。 计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。 有限脉冲响应滤波算法在双执行单元上实现了高性能。
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3.发明授权Method and system for trusted/untrusted digital signal processor debugging operations 失效信任/不信任数字信号处理器调试操作的方法和系统公开(公告)号：US08533530B2
公开(公告)日：2013-09-10
申请号：US11560332
申请日：2006-11-15
申请人： Lucian Codrescu , William C. Anderson , Suresh Venkumahanti , Louis Achille Giannini , Manojkumar Pyla , Xufeng Chen
发明人： Lucian Codrescu , William C. Anderson , Suresh Venkumahanti , Louis Achille Giannini , Manojkumar Pyla , Xufeng Chen
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.
摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在操作与数字信号处理器相关联的核心处理器时，发生信任和不信任的调试操作控制。 调试机制中的调试过程与核心处理器相关联。 核心处理器过程将调试控制的起源确定为可信的调试控制或不可信的调试控制。 在受信任的调试控制的情况下，核心处理器进程向受信任的调试控制提供了第一组功能和特权。 或者，如果调试控制是不可信任的调试控制，则核心处理器进程将不可信任的调试控制提供第二个受限制的特征和特权集，以保持核心处理器进程的安全性和正常运行。
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公开(公告)号：US20120297256A1
公开(公告)日：2012-11-22
申请号：US13112132
申请日：2011-05-20
CPC分类号： G06F12/0893 , G06F11/1064 , G06F12/0646 , Y02D10/13
摘要： Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.
摘要翻译： 用于配置基于页面的存储设备而不具有预先存在的专用元数据的系统和方法。 该方法包括从存储设备的页面的元数据部分读取元数据，以及基于元数据确定页面的特性。 存储器件可以被配置为高速缓存。 元数据可以包括地址标签，使得确定特征可以包括确定页面中是否存在所需信息，并且如果确定存在于页面中则读取所需信息。 元数据还可以包括纠错码（ECC），使得确定特性可以包括检测存在于页面中的数据中存在的错误。 元数据还可以包括目录信息，存储器一致性信息或脏/有效/锁定信息。
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5.发明授权System and method of executing program threads in a multi-threaded processor 有权在多线程处理器中执行程序线程的系统和方法公开(公告)号：US07814487B2
公开(公告)日：2010-10-12
申请号：US11115917
申请日：2005-04-26
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.
摘要翻译： 公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。 第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。 这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。 此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。 当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。
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6.发明授权Method and system for encoding variable length packets with variable instruction sizes 有权用可变指令大小编码可变长度数据包的方法和系统公开(公告)号：US07526633B2
公开(公告)日：2009-04-28
申请号：US11088607
申请日：2005-03-23
CPC分类号： G06F9/30149 , G06F9/3853
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.
摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 该方法和系统编码和处理混合长度（例如，16位和32位）的指令以及包括混合长度指令的指令包。 这包括编码第一长度的多个指令和第二长度的多个指令。 该方法和系统对具有至少一个指令长度位的报头进行编码。 指令位区分第一长度的指令和第二长度的指令，以使相关的DSP在混合流中进行处理。 方法和系统根据指令长度位的内容区分第一长度的指令和第二长度的指令。 标题还包括用于区分指令包中不同长度的指令的位。
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公开(公告)号：US07383420B2
公开(公告)日：2008-06-03
申请号：US11089619
申请日：2005-03-24
CPC分类号： G06F9/35 , G06F9/3851 , G06F9/3853
摘要： A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.
摘要翻译： 处理器可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于第一寄存器输出值访问第二寄存器并获得第二寄存器值， 以及基于所述程序指令将所述第二寄存器值存储到第三寄存器中。 处理器还可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于所述程序指令访问第二寄存器并获得第二寄存器值，以及存储 基于第二寄存器值将第一寄存器值输入到第三寄存器中。
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8.发明申请METHOD AND SYSTEM FOR INSTRUCTION STUFFING OPERATIONS DURING NON-INTRUSIVE DIGITAL SIGNAL PROCESSOR DEBUGGING 有权非侵入式数字信号处理器调试期间的指令运行操作方法与系统公开(公告)号：US20080114972A1
公开(公告)日：2008-05-15
申请号：US11560344
申请日：2006-11-15
申请人： Lucian Codrescu , William C. Anderson , Suresh Venkumahanti , Louis Achille Giannini , Manojkumar Pyla , Xufeng Chen
发明人： Lucian Codrescu , William C. Anderson , Suresh Venkumahanti , Louis Achille Giannini , Manojkumar Pyla , Xufeng Chen
IPC分类号： G06F15/163
CPC分类号： G06F11/362 , G06F11/3656
摘要： Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.
摘要翻译： 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在多线程数字信号处理器的处理流水线中的填充指令提供了在调试机制内操作核心处理器进程和调试过程。 将填充指令写入调试进程注册表，并且调试进程命令寄存器中的填充命令用于标识执行填充指令的多线程数字信号处理器的预定线程。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并指示核心处理器在调试过程中执行填充指令。 核心处理器然后可以与核心处理器进程和调试过程相关联地执行填充指令。
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公开(公告)号：US5619711A
公开(公告)日：1997-04-08
申请号：US267740
申请日：1994-06-29
申请人： William C. Anderson
发明人： William C. Anderson
CPC分类号： G06F7/483 , G06F9/30025 , G06F2207/382
摘要： A data processing system 10 comprises an arbitrary precision number C++ class program code 18, which incorporates arbitrary precision arithmetic. The arbitrary precision number program code 18 resides in a client program 14 and never lose bits of precision by maintaining an internal data structure 16, which holds the data, and by manipulating that data by operators and methods which the program code 18 defines. The program code 18, which is embedded in a client program 14, comprises a method that uses "lazy" storage allocation for transparent data management for the arbitrary precision number in the internal data array 22, a "lazy" arithmetic evaluation for avoiding more costly arithmetic operations, a width method for an optimized significant bit calculation, and a method for efficient determining the number of trailing zeros method for more efficient IEEE floating point math emulation operations.
摘要翻译： 数据处理系统10包括任意精度数C ++类程序代码18，其包含任意精度算术。 任意精度数程序代码18驻留在客户端程序14中，并且通过维护保存数据的内部数据结构16以及通过程序代码18定义的操作符和方法操纵数据，而不会丢失精度位。 嵌入在客户机程序14中的程序代码18包括使用“惰性”存储分配用于内部数据阵列22中的任意精度数字的透明数据管理的方法，用于避免更昂贵的“懒惰”算术评估 算术运算，用于优化的有效位计算的宽度方法，以及用于有效确定用于更有效的IEEE浮点数学仿真操作的尾随零方法的数量的方法。
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公开(公告)号：USD268622S
公开(公告)日：1983-04-12
申请号：US212948
申请日：1980-12-04
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