公开(公告)号：US07318015B2

公开(公告)日：2008-01-08

申请号：US10170615

申请日：2002-06-12

申请人： Gregory G. Carlson ,  Heather Davis ,  John Edmondson Norvell, IV ,  Kevin Lee Zierath ,  Chandra S. Vemulapalli ,  Vidhyaprakash Ramachandran

发明人： Gregory G. Carlson ,  Heather Davis ,  John Edmondson Norvell, IV ,  Kevin Lee Zierath ,  Chandra S. Vemulapalli ,  Vidhyaprakash Ramachandran

IPC分类号： G06F13/10

CPC分类号： H04L41/22 ,  G06F3/0481 ,  H04L41/0233 ,  H04L41/145 ,  Y10S707/99942 ,  Y10S707/99945

摘要： A data model of a modeled environment is maintained within a database. The data model includes data defining a plurality of hierarchically arranged subsets of space within the modeled environment and data defining a plurality of items populating the modeled environment. In response to a first user input selecting a plurality of features of the modeled environment, where each of the selected features is one of the subsets of space or one of the items, a plurality of graphical elements are displayed within a whiteboard window to represent the plurality of user selected features. A control for at least one function is also presented to the user in association with the whiteboard window. In response to a second user input selecting the control for the function, a logical connection between at least two of the plurality of features having corresponding graphical elements within whiteboard window are automatically generated by reference to a rule set. In addition, a graphical element representing the logical connection is displayed within the whiteboard window.

摘要翻译： 在数据库中维护建模环境的数据模型。 数据模型包括定义多个分层布置的建模环境中的空间子集的数据和定义填充建模环境的多个项目的数据。 响应于选择建模环境的多个特征的第一用户输入，其中所选择的特征中的每一个是空间子集或项目之一之一，在白板窗口内显示多个图形元素以表示 多个用户选择的特征。 至少一个功能的控件也与白板窗口相关联地呈现给用户。 响应于选择功能的控制的第二用户输入，通过参考规则集自动生成具有白板窗口内的相应图形元素的多个特征中的至少两个之间的逻辑连接。 此外，表示逻辑连接的图形元素显示在白板窗口中。

公开(公告)号：US20070263757A1

公开(公告)日：2007-11-15

申请号：US11879689

申请日：2007-07-18

申请人： William Dally ,  John Edmondson ,  Ramin Farjad-Rad

发明人： William Dally ,  John Edmondson ,  Ramin Farjad-Rad

IPC分类号： H03D3/24

CPC分类号： H04L7/0331 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/0337 ,  Y10S331/02

摘要： A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.

公开(公告)号：US20060123142A1

公开(公告)日：2006-06-08

申请号：US11005150

申请日：2004-12-06

申请人： Samuel Duncan ,  Wei-Je Huang ,  John Edmondson

发明人： Samuel Duncan ,  Wei-Je Huang ,  John Edmondson

IPC分类号： G06F3/00

CPC分类号： H04L12/66

摘要： A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of a second device by communicating read and write requests across the interconnectivity fabric. Such data transfer can be performed even when the communication protocol of the interconnectivity fabric does not permit such transfers.

摘要翻译： 一种用于通过互连结构提供对等数据传输的方法和装置。 该方法和装置使得第一设备能够通过在互连结构上传递读取和写入请求来向/从第二设备的本地存储器读取和/或写入数据。 即使当互连结构的通信协议不允许这样的传输时，也可以执行这种数据传送。

公开(公告)号：US6145788A

公开(公告)日：2000-11-14

申请号：US450336

申请日：1999-11-29

申请人： Christopher Mouskis ,  Bryan John Edmondson

发明人： Christopher Mouskis ,  Bryan John Edmondson

IPC分类号： B64D39/04 ,  B64D37/00

CPC分类号： B64D39/04

摘要： A drogue assembly (10) for in flight refueling includes a circumferenal array of triangular support arms which carry a drogue parachute (29) which extends circumferentially around their shorter sides. Each support arm is pivoted and mounted on a pivot pin (19) at its apex for pivotal movement in a radial direction. At least alternate ones of the support arms carry leaf springs which extend into pockets (51) formed in the drogue parachute (29). The leaf springs act on the drogue parachute (29) in opposition to air pressure loading on it in flight so that it tends to increase the chord angle of the drogue parachute (29) from the leading edge. Hence the effective area of the drogue parachute in flight is varied automatically above a certain predetermined minimum which depends on the dimensions of the trailing edge so it is reduced as air speed is increased and vice versa.

摘要翻译： 用于飞行加油的锥形组件（10）包括三角形支撑臂的圆周阵列，其具有围绕其较短侧周向延伸的锥形降落伞（29）。 每个支撑臂枢转并安装在其顶点处的枢轴销（19）上，用于在径向方向上枢转运动。 至少交替的支撑臂承载延伸到形成在锥形降落伞（29）中的凹部（51）中的板簧。 叶片弹簧作用在锥形降落伞（29）上，与飞行中的空气压力负载相反，从而倾向于增加锥形降落伞（29）从前缘的和弦角度。 因此，飞行中锥形降落伞的有效面积自动地在一定的最小值以上变化，这取决于后缘的尺寸，因此随着空气速度的增加而减小，反之亦然。

公开(公告)号：US5680544A

公开(公告)日：1997-10-21

申请号：US523297

申请日：1995-09-05

申请人： John Edmondson ,  Scott Taylor

发明人： John Edmondson ,  Scott Taylor

IPC分类号： G06F11/267 ,  G11C29/34 ,  G11C29/38 ,  G11C29/44 ,  G11C29/56 ,  G11C29/00

CPC分类号： G11C29/56 ,  G11C29/34 ,  G11C29/44 ,  G06F11/2236 ,  G11C29/38

摘要： A test system is provided which tests the on chip cache of a microprocessor (CPU). The test system provides test vectors to the CPU in a specified sequences. The CPU then uses its internal general purpose registers to write the vectors the cache memory locations. After writing, the data is read back and compared to an expected value. The results are then stored in other general purpose registers of the CPU. Using the CPUs general purpose registers to record the test results allows the test system to test many cache locations in parallel. Furthermore the test system allows the test to proceed in a fixed number of CPU clock cycles regardless of any detected errors.

摘要翻译： 提供了测试微处理器（CPU）的片上高速缓存的测试系统。 测试系统以指定的顺序向CPU提供测试向量。 CPU然后使用其内部通用寄存器来写入高速缓冲存储器位置的向量。 写入后，数据将被读回并与预期值进行比较。 然后将结果存储在CPU的其他通用寄存器中。 使用CPU通用寄存器来记录测试结果允许测试系统并行测试许多高速缓存位置。 此外，测试系统允许测试以固定数量的CPU时钟周期进行，而不管任何检测到的错误。

公开(公告)号：US07143100B2

公开(公告)日：2006-11-28

申请号：US10170616

申请日：2002-06-12

申请人： Gregory G. Carlson ,  Heather Davis ,  John Edmondson Norvell, IV ,  Kevin Lee Zierath ,  Chandra S. Vemulapalli ,  Vidhyaprakash Ramachandran

发明人： Gregory G. Carlson ,  Heather Davis ,  John Edmondson Norvell, IV ,  Kevin Lee Zierath ,  Chandra S. Vemulapalli ,  Vidhyaprakash Ramachandran

IPC分类号： G06F7/00 ,  G06F17/00 ,  G06F3/00 ,  G06F9/00 ,  G06F15/16

CPC分类号： H04L41/22 ,  G06F3/0481 ,  H04L41/0233 ,  H04L41/145 ,  Y10S707/99942 ,  Y10S707/99945

摘要： A data model of a modeled environment is maintained within a database. The data model includes data defining a plurality of hierarchically arranged subsets of space within the modeled environment and data defining a plurality of items populating the modeled environment. A data processing system displays within a display device at least first and second windows. The first window displays a map of the modeled environment, where the map includes at least one user-selectable graphical element representing one of the plurality of hierarchically arranged subsets of space or one of the plurality of items. In response to a first user input, a graphical element is copied from the first window and displayed within the second window. In response to a second user input selecting the graphical element within the second window, data from the database associated with the subset of space or item represented by the graphical element is presented.

公开(公告)号：US07111155B1

公开(公告)日：2006-09-19

申请号：US09570108

申请日：2000-05-12

申请人： William C. Anderson ,  John Edmondson ,  Jose Fridman ,  Marc Hoffman ,  Russell L. Rivin

发明人： William C. Anderson ,  John Edmondson ,  Jose Fridman ,  Marc Hoffman ,  Russell L. Rivin

IPC分类号： G06F7/38

CPC分类号： G06F9/3867 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30149 ,  G06F9/3824 ,  G06F9/3885

摘要： A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

摘要翻译： 计算核心包括通过存储器接口耦合到存储器的计算块，寻址块和指令定序器。 计算块包括寄存器文件和双执行单元。 执行单元包括用于在执行数字信号计算时增强性能的特征。 计算核心被配置为执行数字信号处理器指令和微控制器指令，同时实现高效的数字信号处理器计算和高代码密度。 有限脉冲响应滤波算法在双执行单元上实现了高性能。

公开(公告)号：US5710124A

公开(公告)日：1998-01-20

申请号：US596203

申请日：1996-02-16

申请人： John Edmondson Peel ,  Bruno Suri

发明人： John Edmondson Peel ,  Bruno Suri

IPC分类号： A61K38/00 ,  A61K38/16 ,  A61P31/00 ,  A61P31/04

CPC分类号： A61K38/164

摘要： A method for treating or preventing mastitis in cows is disclosed. The method contemplates the intramammary injection or dipping the teat with Gallidermin and/or Epidermin or one of their pharmaceutically acceptable acid salts. Gallidermin and/or Epidermin or one of their pharmaceutically acceptable acid salts can be administered prior to infection to effectively suppress the rate, severity, and duration of subsequent bacterial infection, or can be administered subsequent to infection to effectively treat mastitis.

摘要翻译： PCT No.PCT / EP94 / 02567 Sec。 371日期1996年2月16日 102（e）日期1996年2月16日PCT 1994年8月3日PCT PCT。 公开号WO95 / 05844 1995年3月2日公开了一种治疗或预​​防奶牛乳腺炎的方法。 该方法考虑了乳腺内注射或用乳酸剂和/或Epidermin或其药学上可接受的酸式盐之一浸泡乳头。 Gallidermin和/或Epidermin或其药学上可接受的酸盐之一可以在感染之前施用以有效抑制随后的细菌感染的速率，严重性和持续时间，或者可以在感染后施用以有效治疗乳腺炎。

公开(公告)号：US5317720A

公开(公告)日：1994-05-31

申请号：US34581

申请日：1993-03-22

申请人： Rebecca L. Stamm ,  John Edmondson ,  David Archer ,  Samyojita Nadkarni ,  Raymond Strouble

发明人： Rebecca L. Stamm ,  John Edmondson ,  David Archer ,  Samyojita Nadkarni ,  Raymond Strouble

IPC分类号： G06F9/32 ,  F02B75/02 ,  G06F9/38 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0804 ,  G06F12/0811 ,  G06F12/0831 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  F02B2075/025

摘要： A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

摘要翻译： 执行可变长度指令的流水线CPU，并使用各种数据宽度引用存储器。 在分层高速缓存布置中使用回写高速缓存（而不是写通），并且即使由于队列已满而抑制其他访问，也允许回写。 提供单独的队列用于来自存储器的返回数据，并且高速缓存无效，但是顺序或总线事务由指针排列来维护。 CPU与系统总线通信使用的总线协议是挂起类型，由总线标识的总线标识的总线上的事务，总线授权的仲裁与总线上的地址/数据事务同时进行。

公开(公告)号：US08365015B1

公开(公告)日：2013-01-29

申请号：US12853121

申请日：2010-08-09

申请人： Shu-Yi Yu ,  Shane Keil ,  John Edmondson

发明人： Shu-Yi Yu ,  Shane Keil ,  John Edmondson

IPC分类号： G06F11/00

CPC分类号： G06F11/1008 ,  G06F9/3863

摘要： The present disclosure provides memory level error correction methods and apparatus. A memory controller is intermediate the memory devices, such as DRAM chips or memory modules, and a processor, such a graphics processor or a main processor. The memory controller can provide error correction. In an example, the memory controller includes a buffer to store instructions and data for execution by the controller and a replay buffer to store the instructions such that operations can be replayed to prior state before the error. An error detector receives data read from the memory devices and if no error is detected outputs the data. If an error is detected, the error detector signals the memory controller to replay the instructions stored in the replay buffer.

摘要翻译： 本公开提供了存储器级错误校正方法和装置。 存储器控制器在诸如DRAM芯片或存储器模块的存储器件之间，以及诸如图形处理器或主处理器的处理器之间。 存储器控制器可以提供纠错。 在一个示例中，存储器控制器包括一个缓冲器，用于存储用于由控制器执行的指令和数据以及重放缓冲器来存储指令，使得可以在错误之前将操作重播到先前的状态。 错误检测器接收从存储器件读取的数据，如果没有检测到错误则输出数据。 如果检测到错误，则错误检测器通知存储器控制器重放存储在重放缓冲器中的指令。