Invention Grant
- Patent Title: Semiconductor transistor having a stressed channel
- Patent Title (中): 具有应力通道的半导体晶体管
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Application No.: US10626365Application Date: 2003-07-23
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Publication No.: US06861318B2Publication Date: 2005-03-01
- Inventor: Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
- Applicant: Anand Murthy , Robert S. Chau , Tahir Ghani , Kaizad R. Mistry
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/10 ; H01L29/165 ; H01L29/78 ; H01L29/76

Abstract:
A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
Public/Granted literature
- US20040070035A1 Semiconductor transistor having a stressed channel Public/Granted day:2004-04-15
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