发明授权
- 专利标题： Method and structure to reduce defects in integrated circuits and substrates
- 专利标题（中）： 降低集成电路和基板缺陷的方法和结构
-
申请号： US10358565申请日： 2003-02-04
-
公开(公告)号： US06861354B2公开(公告)日： 2005-03-01
- 发明人: Cyprian E. Uzoh , Homayoun Talieh , Bulent M. Basol
- 申请人： Cyprian E. Uzoh , Homayoun Talieh , Bulent M. Basol
- 代理机构： Nu Tool Legal Department
- 主分类号： H01L21/288
- IPC分类号： H01L21/288 ; H01L21/768 ; H01L23/532 ; H01L21/4763
摘要：
A method for forming conductor structures on a semiconductor wafer is provided. The method begins with depositing a seed layer having a substantially consistent thickness over a barrier layer that covers the features and the field regions among them. The process continues with electrodepositing a planar copper layer on the seed layer and subsequently electroetching it until a thinned seed layer remains over the field regions. When another layer of planar copper is deposited on the remaining copper in the features and on the thinned seed layer on the field regions, this structure minimizes stress related defects in the features which occur during a following anneal process.
公开/授权文献
信息查询
IPC分类:
