公开(公告)号：US20110239450A1

公开(公告)日：2011-10-06

申请号：US12906988

申请日：2010-10-18

申请人： Bulent M. Basol ,  Jalal Ashjaee ,  Douglas Young ,  Homayoun Talieh

发明人： Bulent M. Basol ,  Jalal Ashjaee ,  Douglas Young ,  Homayoun Talieh

IPC分类号： H01L31/18

CPC分类号： H01L31/0504 ,  B32B37/1018 ,  B32B37/22 ,  B32B2457/12 ,  H01L31/02 ,  H01L31/048 ,  H01L31/05 ,  Y02E10/50 ,  Y10T29/5313 ,  Y10T29/5317 ,  Y10T29/53261 ,  Y10T29/534 ,  Y10T29/53526

摘要： Described in one embodiment is a system that has a multiple number of different stations for forming solar cell modules. Described in another embodiment is a system that includes a cutting station, a setting station, and an interconnection station to create different series-connected flexible solar cell modules. Described in still another embodiment is a monolithically integrated multi-module power supply.

摘要翻译： 在一个实施例中描述的是具有用于形成太阳能电池模块的多个不同站的系统。 在另一实施例中描述的是包括切割站，设置站和互连站以创建不同串联的柔性太阳能电池模块的系统。 在又一实施例中描述的是单片集成多模块电源。

公开(公告)号：US07704880B1

公开(公告)日：2010-04-27

申请号：US12190082

申请日：2008-08-12

申请人： Cyprian E. Uzoh ,  Bulent M. Basol ,  Hung-Ming Wang ,  Homayoun Talieh

发明人： Cyprian E. Uzoh ,  Bulent M. Basol ,  Hung-Ming Wang ,  Homayoun Talieh

IPC分类号： H01L21/44

CPC分类号： H01L21/2885 ,  C25D5/02 ,  C25D7/123 ,  C25D17/005

摘要： A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as the electroprocessing is performed on the conductive layer.

摘要翻译： 提供了一种用于在基板的表面上制造可移除接触结构以在电加工期间将电从接触构件传导到表面的方法。 该方法包括在表面上形成导电层。 导电层的预定区域被接触层选择性地涂覆，使得当在导电层上进行电处理时，接触构件接触接触层。

公开(公告)号：US07572354B2

公开(公告)日：2009-08-11

申请号：US11445594

申请日：2006-06-01

申请人： Cyprian Emeka Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas W. Young

发明人： Cyprian Emeka Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas W. Young

IPC分类号： C25B9/00 ,  C25D7/00

CPC分类号： B24B37/20 ,  B24B37/046 ,  B24B37/24 ,  B24B37/26 ,  C25D5/06 ,  C25D17/001 ,  C25D17/14 ,  C25F7/00 ,  H01L21/2885 ,  H01L21/76877

摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.

摘要翻译： 本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。 这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。 在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上， 在工件和阳极之间施加电位差。 在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。 在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

公开(公告)号：US20060219573A1

公开(公告)日：2006-10-05

申请号：US11445594

申请日：2006-06-01

申请人： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

发明人： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Douglas Young

IPC分类号： B23H3/00

CPC分类号： B24B37/20 ,  B24B37/046 ,  B24B37/24 ,  B24B37/26 ,  C25D5/06 ,  C25D17/001 ,  C25D17/14 ,  C25F7/00 ,  H01L21/2885 ,  H01L21/76877

摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.

摘要翻译： 本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。 这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。 在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上， 在工件和阳极之间施加电位差。 在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。 在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

公开(公告)号：US20060070885A1

公开(公告)日：2006-04-06

申请号：US11295014

申请日：2005-12-06

申请人： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

发明人： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol

IPC分类号： C25D5/02 ,  C25D5/48

CPC分类号： C25D5/00 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1848 ,  C23C18/31 ,  C25D5/02 ,  C25D5/10 ,  C25D5/22 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L24/11 ,  H01L2221/1089 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3011

摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

公开(公告)号：US20060042934A1

公开(公告)日：2006-03-02

申请号：US11259694

申请日：2005-10-25

申请人： Homayoun Talieh ,  Bulent Basol

发明人： Homayoun Talieh ,  Bulent Basol

IPC分类号： C25D17/00

CPC分类号： H01L21/6715 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/67075

摘要： The present invention is directed to a method and apparatus for plating a surface of a semiconductor workpiece (wafer, flat panel, magnetic films, etc.) using a liquid conductor that makes contact with the outer surface of the workpiece. The liquid conductor is stored in a reservoir and pump through an inlet channel to the liquid chamber. The liquid conductor is injected into a liquid chamber such that the liquid conductor makes contact with the outer surface of the workpiece. An inflatable tube is also provided to prevent the liquid conductor from reaching the back face of the workpiece. A plating solution can be applied to the front face of the workpiece where a retaining ring/seal further prevents the plating solution and the liquid conductor from making contact with each other. In an alternative embodiment, electrical contacts may be formed using an inflatable tube that has either been coated with a conductive material or contains a conductive object. The inflatable tube further provides uniform contact and pressure along the periphery of the workpiece, which may not necessarily be perfectly flat, because the tube can conform according to the shape of the periphery of the workpiece. Further, the present invention can be used to dissolve/etch a metal layer from the periphery of the workpiece.

公开(公告)号：US06974769B2

公开(公告)日：2005-12-13

申请号：US10663318

申请日：2003-09-16

申请人： Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

发明人： Bulent Basol ,  Homayoun Talieh ,  Cyprian Uzoh

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/7684

摘要： Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d1≦0.5d2, with d1 being the first layer thickness and d2 being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d1≦0.3d2.

摘要翻译： 通过特定的工艺制造衬底上的绝缘体层的特征的导电结构。 在该过程中，将导电材料层施加在绝缘体层上，使得导电材料层覆盖与特征相邻的场区域并填充特征本身。 然后通过退火导电材料层来建立覆盖场区的导电材料与填充特征的导电材料之间的晶粒尺寸差。 然后去除过量的导电材料以露出场区并留下导电结构。 施加导电材料层以在场区域上限定第一层厚度，并且在特征中和之上限定第二层厚度。 这些厚度的尺寸使得其中d 1是第一层厚度，d 2 <2 < / SUB>为第二层厚度。 优选地，第一层厚度和第二层厚度的尺寸被确定为使得d 1 = 0.3D 2。

公开(公告)号：US06969456B2

公开(公告)日：2005-11-29

申请号：US10041029

申请日：2001-12-28

申请人： Konstantin Volodarsky ,  Boguslaw A. Nagorski ,  Rimma Volodarsky ,  Douglas W. Young ,  Cyprian Uzoh ,  Homayoun Talieh

发明人： Konstantin Volodarsky ,  Boguslaw A. Nagorski ,  Rimma Volodarsky ,  Douglas W. Young ,  Cyprian Uzoh ,  Homayoun Talieh

IPC分类号： C25D7/12 ,  H01L21/00 ,  H01L21/02 ,  H01L21/3063 ,  C25F3/00 ,  B08B3/04

CPC分类号： H01L21/6719 ,  C25D7/12 ,  C25D17/001 ,  H01L21/67028 ,  Y10S134/902

摘要： The present invention relates to a containment chamber that is used for carrying out multiple processing steps such as depositing on, polishing, etching, modifying, rinsing, cleaning, and drying a surface on the workpiece. In one example of the present invention, the chamber is used to electro chemically mechanically deposit a conductive material on a semiconductor wafer. The same containment chamber can then be used to rinse and clean the same wafer. As a result, the present invention eliminates the need for separate processing stations for depositing the conductive material and cleaning the wafer. Thus, with the present invention, costs and physical space are reduced while providing an efficient apparatus and method for carrying out multiple processes on the wafer surface using a containment chamber.

摘要翻译： 本发明涉及一种用于进行多个处理步骤的容纳室，例如沉积，抛光，蚀刻，改性，漂洗，清洁和干燥工件上的表面。 在本发明的一个实例中，室用于在半导体晶片上化学机械地沉积导电材料。 然后可以使用相同的容纳室来冲洗和清洁相同的晶片。 结果，本发明消除了对用于沉积导电材料和清洁晶片的单独处理站的需要。 因此，利用本发明，降低了成本和物理空间，同时提供了使用容纳室在晶片表面上执行多个工艺的有效的装置和方法。

公开(公告)号：US06905588B2

公开(公告)日：2005-06-14

申请号：US09905335

申请日：2001-07-13

申请人： Cyprian Emeka Uzoh ,  Homayoun Talieh ,  Bulent Basol

发明人： Cyprian Emeka Uzoh ,  Homayoun Talieh ,  Bulent Basol

IPC分类号： C25D3/02 ,  C23C28/00 ,  C25D5/10 ,  C25D7/12 ,  H01L21/288 ,  H01L21/304 ,  H01L21/60 ,  H01L21/768 ,  C25D5/00 ,  B23H3/00

CPC分类号： C25D5/00 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1848 ,  C23C18/31 ,  C25D5/02 ,  C25D5/10 ,  C25D5/22 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L24/11 ,  H01L2221/1089 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3011

摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

摘要翻译： 本发明涉及一种制造高性能芯片互连和封装的方法，该方法通过提供以更高效和省时的方式在衬底的空腔中沉积导电材料的方法。 这是通过从衬底的顶表面选择性地去除种子层的部分，然后在衬底的空腔中沉积导电材料，其中种子层的部分保留在空腔中。 另一种方法包括在衬底的顶表面上形成氧化物层，使得导电材料可以沉积在空腔中，而不会在衬底的顶表面上形成材料。 本发明还公开了用于形成多级互连的方法和相应的结构。

公开(公告)号：US06902659B2

公开(公告)日：2005-06-07

申请号：US10238665

申请日：2002-09-09

申请人： Homayoun Talieh

发明人： Homayoun Talieh

IPC分类号： B24B37/04 ,  C25D5/02 ,  C25D5/06 ,  C25D5/22 ,  H01L21/288 ,  H01L21/321 ,  C25F3/16

CPC分类号： C25D5/02 ,  B24B37/20 ,  C25D5/06 ,  C25D5/22 ,  H01L21/2885 ,  H01L21/3212

摘要： The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermine area by mechanically polishing the other areas while the conductive material is being applied.

摘要翻译： 本发明将导电材料从电解质溶液沉积到晶片的预定区域。 在进行该应用时使用的步骤包括：当晶片设置在阴极和阳极之间时，使用设置在晶片表面上的电解质溶液将导电材料施加到晶片的预定区域，并且防止 导电材料通过在施加导电材料的同时机械抛光其它区域而不是预定区域的区域。