发明授权
US06862223B1 MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
有权
单声道，组合非易失性存储器允许使用统一的单元结构和技术与解码器和布局的新方案在单元格阵列中无干扰和分离的字节，页面和块写入
- 专利标题： MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT
- 专利标题（中）： 单声道，组合非易失性存储器允许使用统一的单元结构和技术与解码器和布局的新方案在单元格阵列中无干扰和分离的字节，页面和块写入
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申请号： US10223208申请日： 2002-08-19
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公开(公告)号： US06862223B1公开(公告)日： 2005-03-01
- 发明人: Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
- 申请人： Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
- 申请人地址： US CA San Jose
- 专利权人： Aplus Flash Technology, Inc.
- 当前专利权人： Aplus Flash Technology, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 George O. Saile; Stephen B. Ackerman; Rosemary L.S. Pike
- 主分类号： G11C11/34
- IPC分类号： G11C11/34 ; G11C16/04 ; H01L27/115
摘要：
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.