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    Byte-programmable flash memory having counters and secondary storage for disturb control during program and erase operations
    4.
    发明授权
    Byte-programmable flash memory having counters and secondary storage for disturb control during program and erase operations 有权
    字节可编程闪存，具有计数器和辅助存储器，用于在编程和擦除操作期间进行干扰控制

    公开(公告)号：US6005810A

    公开(公告)日：1999-12-21

    申请号：US131566

    申请日：1998-08-10

    申请人： Koucheng Wu

    发明人： Koucheng Wu

    IPC分类号： G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3427 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

    摘要： A byte-programmable/byte-erasable flash memory system having on-chip counters and secondary storage for word line and bit line disturbance control during program and erase operations. The counters count the numbers of program/erase cycles and compare them with empirically pre-determined counter limits; when the program/erase count exceeds the counter limit, the data then carried in the system are temporarily transferred onto the secondary storage while the memory array is refreshed and the counters are reset. The lifetime of the resulting flash memory system is improved because of decreased erase and program stresses in the memory array.

    摘要翻译： 一种字节可编程/字节可擦除闪存系统，具有片上计数器和辅助存储器，用于在编程和擦除操作期间进行字线和位线干扰控制。 计数器对程序/擦除周期数进行计数，并将其与经验预定的计数器限值进行比较; 当程序/擦除计数超过计数器限制时，系统中承载的数据将被暂时转移到辅助存储器上，同时更新存储器阵列并重置计数器。 由于存储器阵列中的擦除和程序应力减小，所以闪存系统的寿命得到改善。

    Apparatus and method for programming antifuse structures
    5.
    发明授权
    Apparatus and method for programming antifuse structures 失效
    用于编程反熔丝结构的装置和方法

    公开(公告)号：US5753540A

    公开(公告)日：1998-05-19

    申请号：US699867

    申请日：1996-08-20

    申请人： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

    发明人： Koucheng Wu ,  Ivan Sanchez ,  Yu-Pin Han ,  Ying-Tsong Loh

    IPC分类号： H01L23/525 ,  H01L21/82

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

    摘要翻译： 公开了一种用于编程反熔丝结构的方法。 反熔丝结构通过在底部和顶部电极之间施加具有交流电脉冲的交流电来编程，以产生穿过夹在电极之间的反熔丝的导电路径。 由于由于每个交流脉冲而产生的电子流，传导路径增量地形成，从而在反熔丝材料的基本中心部分处限定导电路径。

    SCHOTTKY BARRIER QUANTUM WELL RESONANT TUNNELING TRANSISTOR
    6.
    发明申请
    SCHOTTKY BARRIER QUANTUM WELL RESONANT TUNNELING TRANSISTOR 有权
    SCHOTTKY BARRIER量子阱谐振隧道晶体管

    公开(公告)号：US20100102298A1

    公开(公告)日：2010-04-29

    申请号：US12258425

    申请日：2008-10-26

    申请人： Koucheng Wu

    发明人： Koucheng Wu

    IPC分类号： H01L29/15

    CPC分类号： H01L29/7322 ,  H01L27/0605 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0821 ,  H01L29/152 ,  H01L29/20 ,  H01L29/73 ,  H01L29/7308

    摘要： A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than 100 Å. A first Schottky barrier junction is formed at the interface of the first semiconductor barrier region and the one or more conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.

    摘要翻译： 半导体晶体管器件包括一个或多个导电基极区域，第一半导体势垒区域，第二半导体势垒区域，导电发射极区域和导电收集区域。 第一半导体势垒区域或第二半导体势垒区域的尺寸小于100埃。 在第一半导体势垒区域和一个或多个导电基极区域的界面处形成第一肖特基势垒结。 在第二半导体阻挡区域和一个或多个导电基极区域的界面处形成第二肖特基势垒结。 在导电发射极区域和第一半导体势垒区域的界面处形成第三肖特基势垒结。 第四肖特基势垒结形成在导电集电区和第二半导体势垒区的界面处。

    Nor-type channel-program channel-erase contactless flash memory on SOI
    7.
    发明授权
    Nor-type channel-program channel-erase contactless flash memory on SOI 失效
    SOI上的非类型通道编程通道擦除非接触式闪存

    公开(公告)号：US07495283B2

    公开(公告)日：2009-02-24

    申请号：US11193653

    申请日：2005-08-01

    申请人： Koucheng Wu

    发明人： Koucheng Wu

    IPC分类号： H01L29/788

    CPC分类号： G11C16/3404 ,  G11C11/5628 ,  G11C16/0416 ,  G11C16/0491 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7881

    摘要： A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.

    摘要翻译： 具有电可擦除可编程只读存储器（EEPROM）的半导体器件包括以行和列布置并构造在绝缘体上硅晶片上的EEPROM存储器单元的非接触阵列。 每个EEPROM存储单元包括漏极区域，源极区域，栅极区域和体区域。 半导体器件还包括多条栅极线，每条栅极线连接一行EEPROM存储器单元的栅极区域，多个体线，每条主体线连接EEPROM存储单元列的主体区域;多个源极线，每条源极线连接源极 一列EEPROM存储单元的区域，以及各自连接EEPROM存储单元列的漏区的多条漏极线。 源极线和漏极线为掩埋线，并且EEPROM存储单元的列的源极区域和漏极区域与EEPROM存储器单元的相邻列的源极区域和漏极区域绝缘。