发明授权
- 专利标题： Wiring structure of semiconductor device
- 专利标题（中）： 半导体器件的接线结构
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申请号： US10401791申请日： 2003-03-31
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公开(公告)号： US06864583B2公开(公告)日： 2005-03-08
- 发明人: Noriaki Matsunaga , Takamasa Usui , Sachiyo Ito
- 申请人： Noriaki Matsunaga , Takamasa Usui , Sachiyo Ito
- 申请人地址： JP Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Kawasaki
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JP11-076350 19990319
- 主分类号： H01L21/768
- IPC分类号： H01L21/768 ; H01L23/485 ; H01L23/532 ; H01L23/48 ; H01L21/4763 ; H01L23/52 ; H01L29/40
摘要：
A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.
公开/授权文献
- US20030205814A1 Wiring structure of semiconductor device 公开/授权日：2003-11-06
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