公开(公告)号：US08758841B2

公开(公告)日：2014-06-24

申请号：US10510497

申请日：2003-04-11

申请人： Shunji Hayashi ,  Shigeru Aizawa ,  Naoki Taketomo ,  Tadashi Nakatsubo ,  Noriaki Matsunaga ,  Katsunori Kimura

发明人： Shunji Hayashi ,  Shigeru Aizawa ,  Naoki Taketomo ,  Tadashi Nakatsubo ,  Noriaki Matsunaga ,  Katsunori Kimura

IPC分类号： A23C9/12

CPC分类号： A23C19/0323 ,  A23Y2220/37

摘要： Natural cheese which comprises a lactic acid bacterium belonging to Lactobacillus gasseri having a disinfection potency against Helicobacter pylori, and a method for producing the natural cheese.

摘要翻译： 天然乳酪，其含有具有对幽门螺杆菌的消毒效力的属于加氏乳杆菌的乳酸菌，以及天然干酪的制造方法。

公开(公告)号：US08601686B2

公开(公告)日：2013-12-10

申请号：US12899762

申请日：2010-10-07

申请人： Noriaki Matsunaga ,  Hiroki Asou ,  Mineo Yamamoto ,  Mamoru Kawakubo

发明人： Noriaki Matsunaga ,  Hiroki Asou ,  Mineo Yamamoto ,  Mamoru Kawakubo

IPC分类号： B23P6/00

CPC分类号： F04D13/0633 ,  F04D29/628

摘要： A manufacturing method of a water circulating pump including a shaft, a pump part having a first casing in which a first concavity is formed for receiving one end portion of the shaft to restrain rotation of the shaft. A stator part has a second casing in which a second concavity is formed for receiving another end portion of the shaft to restrain rotation of the shaft and a stator for rotating a rotor by electromagnetic interaction. The method includes inserting the another end portion of the shaft into a position corresponding to the second concavity of a mold for molding the second casing, and molding the second casing by injecting a thermoplastic resin into the mold for molding the second casing into which the another end portion of the shaft has been inserted.

摘要翻译： 一种包括轴的水循环泵的制造方法，具有第一壳体的泵部，所述第一壳体形成有第一凹部，用于容纳所述轴的一个端部以抑制所述轴的旋转。 定子部分具有第二壳体，其中形成有第二凹部，用于容纳轴的另一端部以限制轴的旋转，以及通过电磁相互作用使转子旋转的定子。 该方法包括将轴的另一个端部插入与用于模制第二壳体的模具的第二凹部相对应的位置，并且通过将热塑性树脂注射到用于模制第二壳体的模具中来模制第二壳体， 轴的端部已插入。

公开(公告)号：US07996813B2

公开(公告)日：2011-08-09

申请号：US12654865

申请日：2010-01-07

申请人： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kenji Yoshida ,  Noriaki Matsunaga

发明人： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kenji Yoshida ,  Noriaki Matsunaga

IPC分类号： G06F15/04

CPC分类号： G06F17/5068

摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

摘要翻译： 一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

公开(公告)号：US20110006425A1

公开(公告)日：2011-01-13

申请号：US12726520

申请日：2010-03-18

申请人： Makoto Wada ,  Noriaki Matsunaga ,  Yosuke Akimoto

发明人： Makoto Wada ,  Noriaki Matsunaga ,  Yosuke Akimoto

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate and containing a wiring trench; a first catalyst layer provided directly or via another member on side and bottom surfaces of the wiring trench; and a first graphene layer provided in the wiring trench so as to be along the side and bottom surface of the wiring trench, the first graphene layer being provided on the first catalyst layer so as to be in contact with the first catalyst layer.

摘要翻译： 根据一个实施例的半导体器件包括：半导体衬底; 绝缘膜，设置在所述半导体基板上并且包含布线沟槽; 第一催化剂层，直接地或经由布线沟槽的侧表面和底表面上的另一个构件提供; 以及设置在所述布线沟槽中以沿着所述布线沟槽的侧面和底面的第一石墨烯层，所述第一石墨烯层设置在所述第一催化剂层上以与所述第一催化剂层接触。

公开(公告)号：US20100237501A1

公开(公告)日：2010-09-23

申请号：US12726604

申请日：2010-03-18

申请人： Hideyuki Tomizawa ,  Noriaki Matsunaga ,  Tadayoshi Watanabe ,  Shiro Mishima ,  Masako Kodera

发明人： Hideyuki Tomizawa ,  Noriaki Matsunaga ,  Tadayoshi Watanabe ,  Shiro Mishima ,  Masako Kodera

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76826 ,  H01L21/3105 ,  H01L21/76832 ,  H01L21/76849 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device includes forming an insulating film including silicon, oxygen, carbon and hydrogen above a semiconductor substrate, forming a wiring trench in the insulating film, forming a metal film to be a metal wiring on the insulating film such that the metal film is provided in the wiring trench, forming the metal wiring by removing the metal film outside the wiring trench, performing a hydrophobic treatment to the surface of the insulating film after the forming the metal wiring, and forming a metal cap selectively on an upper surface of the metal wiring by plating after the performing the hydrophobic treatment.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成包括硅，氧，碳和氢的绝缘膜，在绝缘膜中形成布线沟槽，在绝缘膜上形成金属膜作为金属布线，使得 金属膜设置在布线沟槽中，通过去除布线沟槽外的金属膜形成金属布线，在形成金属布线之后对绝缘膜的表面进行疏水处理，并在上部选择性地形成金属帽 在执行疏水处理之后通过电镀的金属布线的表面。

公开(公告)号：US20100181673A1

公开(公告)日：2010-07-22

申请号：US12652204

申请日：2010-01-05

申请人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US20080308945A1

公开(公告)日：2008-12-18

申请号：US12137623

申请日：2008-06-12

申请人： Takeshi Ishigaki ,  Noriaki Matsunaga

发明人： Takeshi Ishigaki ,  Noriaki Matsunaga

IPC分类号： H01L23/48

CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit according to an example of the present invention includes a first interconnect extending in a first direction, a second interconnect arranged over the first interconnect and extending in a second direction intersecting the first direction, a first via for connecting a first contact part of the first interconnect and a second contact part of the second interconnect, and a second via for connecting a third contact part of the first interconnect and a fourth contact part of the second interconnect. The first and third contact parts are arranged by being aligned in the first direction, and the second and fourth contact parts are arranged by being aligned in the second direction.

摘要翻译： 根据本发明的示例的半导体集成电路包括：沿第一方向延伸的第一互连，布置在第一互连上并沿与第一方向相交的第二方向延伸的第二互连;第一通孔，用于连接第一接触部分 和第二互连的第二接触部分，以及用于连接第一互连的第三接触部分和第二互连的第四接触部分的第二通孔。 第一接触部和第三接触部通过沿第一方向排列配置，第二接触部和第四接触部通过沿第二方向对准而配置。

公开(公告)号：US20080308939A1

公开(公告)日：2008-12-18

申请号：US12120720

申请日：2008-05-15

申请人： Noriaki MATSUNAGA

发明人： Noriaki MATSUNAGA

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of first group wiring layers laminated on a substrate, and each of the first group wiring layers having a wire formed with a first minimum wire width and a main dielectric film portion; and a plurality of second group wiring layers laminated on a top layer of the plurality of first group wiring layers and each of the second group wiring layers having a wire formed with a second minimum wire width greater than the first minimum wire width and a main dielectric film portion, wherein a main dielectric film portion in a bottom layer of the plurality of second group wiring layers has a relative dielectric constant which is substantially identical to a relative dielectric constant of main dielectric film portions of the other second group wiring layers, and Young's modulus of the main dielectric film portion in the bottom layer of the plurality of second group wiring layers is smaller than those of the main dielectric film portions of the other second group wiring layers and larger than those of main dielectric film portions of the first group wiring layers.

摘要翻译： 半导体器件包括层叠在基板上的多个第一组布线层，并且每个第一组布线层具有形成有第一最小布线宽度的线和主电介质膜部分; 以及多个第二组布线层，层叠在多个第一组布线层的顶层上，并且每个第二组布线层具有形成有大于第一最小布线宽度的第二最小布线宽度的导线，以及主电介质 其中，所述多个第二组布线层的底层中的主电介质膜部分具有与其它第二组布线层的主电介质膜部分的相对介电常数基本相同的相对介电常数，并且Young 多个第二组布线层的底层中的主电介质膜部分的模量小于其它第二组布线层的主电介质膜部分的模量，并且大于第一组布线的主电介质膜部分的模量 层。

公开(公告)号：US07335316B2

公开(公告)日：2008-02-26

申请号：US10766961

申请日：2004-01-30

申请人： Takako Takei ,  Takeshi Araki ,  Takanori Sone ,  Hiroyuki Teramoto ,  Takayuki Hanaki ,  Noriaki Matsunaga

发明人： Takako Takei ,  Takeshi Araki ,  Takanori Sone ,  Hiroyuki Teramoto ,  Takayuki Hanaki ,  Noriaki Matsunaga

IPC分类号： H01F1/00

CPC分类号： H01F1/083 ,  H01F1/0578 ,  H01F1/113 ,  H01F41/0273

摘要： A plastic magnet precursor which can be supplied in molding a plastic magnet with a constant composition without requiring kneading in which a resin is melted and sheared. Through injection molding using the precursor, a plastic magnet having little deterioration of magnetic properties and a small variation in quality is obtained. The plastic magnet precursor according to the present invention includes an Nd—Fe—B isotropic magnet powder and a ferrite anisotropic magnet powder subjected to coating with a titanate coupling agent, and a thermoplastic resin powder adhered around the magnet powder.

摘要翻译： 一种塑料磁体前体，可以在不需要捏合的情况下以恒定的组成成型塑料磁体来供应，其中树脂被熔化和剪切。 通过使用前体的注射成型，可以获得磁性能变差小，质量变化小的塑料磁体。 根据本发明的塑料磁体前体包括Nd-Fe-B各向同性磁体粉末和经过钛酸酯偶联剂涂覆的铁素体各向异性磁体粉末和粘附在磁体粉末附近的热塑性树脂粉末。

公开(公告)号：US20070158849A1

公开(公告)日：2007-07-12

申请号：US11619338

申请日：2007-01-03

申请人： Kazuyuki Higashi ,  Noriaki Matsunaga

发明人： Kazuyuki Higashi ,  Noriaki Matsunaga

IPC分类号： H01L23/52

CPC分类号： G06F17/5068 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to an embodiment of the present invention has: a semiconductor substrate; an interlayer insulating film formed above the semiconductor substrate; a protective film formed on the interlayer insulating film, the protective film having a higher density than that of the interlayer insulating film; at least one of a wiring and a dummy wiring formed in the interlayer insulating film and the protective film; and a separation wall formed within the interlayer insulating film so as to surround a low density region to separate the low density region from other regions, a sum of covering densities of the wiring and the dummy wiring being lower than a predetermined prescribed value in the low density region.

摘要翻译： 根据本发明的实施例的半导体器件具有：半导体衬底; 形成在半导体衬底上的层间绝缘膜; 形成在所述层间绝缘膜上的保护膜，所述保护膜的密度高于所述层间绝缘膜的密度; 在层间绝缘膜和保护膜中形成的布线和虚拟布线中的至少一个; 以及形成在层间绝缘膜内的隔离壁，以便围绕低密度区域以将低密度区域与其他区域分离，布线和虚拟布线的覆盖密度之和低于低于预定的规定值 密度区域。