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    Semiconductor device with protective layer
    4.
    发明授权
    Semiconductor device with protective layer 失效
    具有保护层的半导体器件

    公开(公告)号：US06642622B2

    公开(公告)日：2003-11-04

    申请号：US10369517

    申请日：2003-02-21

    申请人： Takamasa Usui ,  Sachiyo Ito

    发明人： Takamasa Usui ,  Sachiyo Ito

    IPC分类号： H01L2348

    CPC分类号： H01L23/5329 ,  H01L23/4334 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a substrate and a first insulating film provided above the semiconductor substrate. A first interconnecting layer is provided on the first insulating film. A second insulating film is provided above the first interconnecting layer and the first insulating layer. A first protective film is provided above the second insulating film and composed substantially of metal material. A second protective film is composed substantially of a passivity of the metal material and provided on a surface of the first protective film.

    摘要翻译： 半导体器件包括衬底和设置在半导体衬底之上的第一绝缘膜。 第一互连层设置在第一绝缘膜上。 第二绝缘膜设置在第一互连层和第一绝缘层之上。 第一保护膜设置在第二绝缘膜之上并且基本上由金属材料构成。 第二保护膜基本上由金属材料的无源性组成并设置在第一保护膜的表面上。

    Semiconductor device
    5.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20050167842A1

    公开(公告)日：2005-08-04

    申请号：US10974922

    申请日：2004-10-28

    申请人： Naofumi Nakamura ,  Noriaki Matsunaga ,  Sachiyo Ito ,  Masahiko Hasunuma ,  Takeshi Nishioka

    发明人： Naofumi Nakamura ,  Noriaki Matsunaga ,  Sachiyo Ito ,  Masahiko Hasunuma ,  Takeshi Nishioka

    IPC分类号： H01L23/52 ,  H01L21/00 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/00 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01L27/10 ,  H01L29/40

    CPC分类号： H01L23/564 ,  H01L23/522 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.

    摘要翻译： 半导体器件包括设置在半导体衬底之上的第一绝缘层。 第一绝缘层包括基本上由相对介电常数小于3的材料组成的层。第一绝缘层包括由插头和布线组成的第一整体结构。 布线的上表面与第一绝缘层的上表面齐平，插头的下表面与第一绝缘层的下表面齐平。 区域保护构件由由插头和布线组成的第二整体结构形成。 第二整体结构从第一绝缘层的上表面延伸到第一绝缘层的下表面。 区域保护构件围绕由水平面上的边界区划分的第一至第n区域（n为自然2以上）中的一个。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07339256B2

    公开(公告)日：2008-03-04

    申请号：US10974922

    申请日：2004-10-28

    申请人： Naofumi Nakamura ,  Noriaki Matsunaga ,  Sachiyo Ito ,  Masahiko Hasunuma ,  Takeshi Nishioka

    发明人： Naofumi Nakamura ,  Noriaki Matsunaga ,  Sachiyo Ito ,  Masahiko Hasunuma ,  Takeshi Nishioka

    IPC分类号： H01L29/72

    CPC分类号： H01L23/564 ,  H01L23/522 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.

    摘要翻译： 半导体器件包括设置在半导体衬底之上的第一绝缘层。 第一绝缘层包括基本上由相对介电常数小于3的材料组成的层。第一绝缘层包括由插头和布线组成的第一整体结构。 布线的上表面与第一绝缘层的上表面齐平，插头的下表面与第一绝缘层的下表面齐平。 区域保护构件由由插头和布线组成的第二整体结构形成。 第二整体结构从第一绝缘层的上表面延伸到第一绝缘层的下表面。 区域保护构件围绕由水平面上的边界区划分的第一至第n区域（n为自然2以上）中的一个。

    Stress analysis method, wiring structure design method, program, and semiconductor device production method
    8.
    发明申请
    Stress analysis method, wiring structure design method, program, and semiconductor device production method 有权
    应力分析方法，接线结构设计方法，程序和半导体器件的制造方法

    公开(公告)号：US20070204243A1

    公开(公告)日：2007-08-30

    申请号：US11703218

    申请日：2007-02-07

    申请人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

    发明人： Sachiyo Ito ,  Masahiko Hasunuma ,  Hisashi Kaneko

    IPC分类号： G06F17/50 ,  G06F17/10 ,  G06F19/00 ,  G01L19/00

    CPC分类号： G06F17/5018 ,  G06F17/5068 ,  G06F2217/80 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

    摘要翻译： 提供一种应力分析方法，包括：通过使用分割单元将芯片的内部划分为多个分析区域，通过使用复合特性导出单元导出多个分析区域的物理属性值的复合特性 基于多个分析区域中的每一个的布线结构数据，分析包括在分析区域中的材料，并且基于多个分析区域中的每一个，分别对每个分析区域进行复合，并且通过使用应力分析单元来创建三维模型 使用每个分析区域作为元素的有限元法，将复合属性应用于每个元素，并进行应力分析。

    Semiconductor wiring device
    9.
    发明授权
    Semiconductor wiring device 有权

    公开(公告)号：US06580171B2

    公开(公告)日：2003-06-17

    申请号：US10085067

    申请日：2002-03-01

    申请人： Sachiyo Ito ,  Masahiko Hasunuma

    发明人： Sachiyo Ito ,  Masahiko Hasunuma

    IPC分类号： H01L23522

    CPC分类号： H01L23/5329 ,  H01L23/53223 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A semiconductor device is structured to include a wiring made of Al, a first insulation film made of silicon oxide including an organic content formed in contact with an upper surface of the wiring, and a second insulation film formed in contact with an upper surface of the first insulation film and made of an F-added SiO2 film having a higher Young's modulus than that of the first insulation film. The wiring has a film thickness dM of 400 nm, the first insulation film has a film thickness ds of 400 nm, and the second insulation film has a film thickness dh of 10 nm.

    Method for manufacturing high reliability interconnection having diffusion barrier layer
    10.
    发明授权
    Method for manufacturing high reliability interconnection having diffusion barrier layer 失效
    制造具有扩散阻挡层的高可靠性互连的方法

    公开(公告)号：US06403462B1

    公开(公告)日：2002-06-11

    申请号：US09321848

    申请日：1999-05-28

    申请人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Shohei Shima ,  Sachiyo Ito

    发明人： Masahiko Hasunuma ,  Hisashi Kaneko ,  Shohei Shima ,  Sachiyo Ito

    IPC分类号： H01L214763

    CPC分类号： H01L21/76847 ,  H01L21/32051 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

    摘要翻译： 本发明的半导体器件制造方法具有在半导体衬底上形成层间绝缘膜的步骤，在层间绝缘膜中形成互连槽的步骤，用导电膜填充互连槽的内部的步骤 由第一物质制成并且比互连槽的深度厚，在Al膜同时或在Al膜形成之后热稳定晶粒尺寸的步骤，形成 Al膜上的Cu膜，通过使Cu选择性地扩散到Al膜的晶粒边界并允许θ相层分割Al膜，在Al膜的晶粒边界中选择性地形成θ相层的步骤 在互连槽中成为比Blech临界长度短的精细Al互连，以及除去Interconnec外部的Al膜和Cu膜的步骤 沟槽。