DRAM cell structure with buried surrounding capacitor and process for manufacturing the same

Invention Grant

US06875653B2 DRAM cell structure with buried surrounding capacitor and process for manufacturing the same 有权

Title translation: 具有埋置周围电容器的DRAM单元结构及其制造方法

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Patent Title: DRAM cell structure with buried surrounding capacitor and process for manufacturing the same
Patent Title (中): 具有埋置周围电容器的DRAM单元结构及其制造方法
Application No.: US10210031

Application Date: 2002-08-02
Publication No.: US06875653B2

Publication Date: 2005-04-05
Inventor: Ting-Shing Wang
Applicant: Ting-Shing Wang
Applicant Address: TW Hsinchu
Assignee: ProMOS Technologies Inc.
Current Assignee: ProMOS Technologies Inc.
Current Assignee Address: TW Hsinchu
Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
Main IPC: H01L21/8242
IPC: H01L21/8242 ; H01L27/02 ; H01L27/108

DRAM cell structure with buried surrounding capacitor and process for manufacturing the same

Abstract:

A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract(Chinese):

一种存储器件，包括半导体衬底和存储器单元阵列，每个单元与相邻单元电隔离并且包括由衬底形成的岛，所述岛具有顶部部分和至少一个侧壁部分，并且间隔开通过基板上的底面从其他岛形成与该侧壁部分相邻的电容器，以及形成在该岛的顶部的晶体管，该晶体管包括形成于顶部表面的栅极氧化层，栅极形成在栅极氧化物层上，以及形成在顶部的第一和第二扩散区域，第一扩散区域与第二扩散区域间隔开。

Public/Granted literature

US20040021162A1 DRAM cell structure with buried surrounding capacitor and process for manufacturing the same Public/Granted day:2004-02-05

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8242	.........动态随机存取存储结构（DRAM）