公开(公告)号：US08103978B2

公开(公告)日：2012-01-24

申请号：US12198121

申请日：2008-08-26

申请人： Chun-Yu Lin ,  Chia-Jung Liou ,  Cheng-Hung Ku ,  Feng-Yuan Chiu ,  Chun-Kuang Lin ,  Chih-Chiang Huang

发明人： Chun-Yu Lin ,  Chia-Jung Liou ,  Cheng-Hung Ku ,  Feng-Yuan Chiu ,  Chun-Kuang Lin ,  Chih-Chiang Huang

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.

摘要翻译： 提供了一种用于建立用于制造器件的掩模图案的散射线规则的方法。 该方法描述如下。 首先，根据掩模图案建立至少一个图像模拟模型，以及基于掩模图案用于制造该装置的工艺参考组。 接下来，将多个散射条参考集合应用于图像模拟模型，以分别生成多个模拟图像。 此外，根据筛选标准，将模拟图像的一部分选择为多个候选布局。 接下来，根据选择规则将候选布局之一确定为图案布局，并且将与图案布局相对应的散射条参考集确定为掩模图案的散射条规则。

公开(公告)号：US07910429B2

公开(公告)日：2011-03-22

申请号：US10821100

申请日：2004-04-07

申请人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Ming Yang

发明人： Zhong Dong ,  Chuck Jang ,  Ching-Hwa Chen ,  Chunchieh Huang ,  Jin-Ho Kim ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao ,  George Kovall ,  Steven Ming Yang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/7881

摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

摘要翻译： 通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分 材料 堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。 结果，氧化不沿着侧壁的多层高度均匀地进行。 本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。 更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为 深深地通过侧壁的已氧化层，例如氧化硅层。 结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

公开(公告)号：US07871884B2

公开(公告)日：2011-01-18

申请号：US12195365

申请日：2008-08-20

申请人： Jung-Wu Chien

发明人： Jung-Wu Chien

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L29/66181

摘要： A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capacitors includes a lower electrode, an upper electrode, and a capacitor dielectric layer. A device isolation layer is formed in the first mask layer and the substrate for defining an active region. The first mask layer is removed for exposing the substrate, and a semiconductor layer is formed on the exposed substrate. The semiconductor layer and the substrate are patterned for forming trenches, and the bottom of the trench is adjacent to the upper electrodes of the trench capacitor. Gate structures filling into the trenches are formed on the substrate. A doped region is formed in the substrate adjacent to a side of the gate structure.

摘要翻译： 一种用于制造DRAM的方法包括首先提供形成图案化的第一掩模层和被图案化的第一掩模层暴露的深沟槽的衬底。 深沟槽电容器形成在深沟槽中，并且每个深沟槽电容器包括下电极，上电极和电容器介电层。 在第一掩模层和衬底中形成器件隔离层，用于限定有源区。 去除第一掩模层以暴露衬底，并且在暴露的衬底上形成半导体层。 图案化半导体层和衬底以形成沟槽，并且沟槽的底部与沟槽电容器的上部电极相邻。 填充到沟槽中的栅极结构形成在衬底上。 掺杂区域形成在与栅极结构的一侧相邻的衬底中。

公开(公告)号：US20100213432A1

公开(公告)日：2010-08-26

申请号：US12468699

申请日：2009-05-19

申请人： Jen-Chi Chuang ,  Ming-Jeng Huang ,  Chien-Min Lee ,  Jia-Yo Lin ,  Min-Chih Wang

发明人： Jen-Chi Chuang ,  Ming-Jeng Huang ,  Chien-Min Lee ,  Jia-Yo Lin ,  Min-Chih Wang

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1233 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

摘要： A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.

摘要翻译： 公开了一种形成相变存储器件的方法。 提供具有底部电极的基板。 在底部电极上形成加热电极和电介质层，其中加热电极被电介质层包围。 蚀刻加热电极以在电介质层中形成凹陷。 相变材料沉积在介电层上，填充到凹槽中。 抛光相变材料以除去超过介电层表面的一部分相变材料，并将相变层限制在电介质层的凹槽中。 在相变层和电介质层上形成顶部电极。

公开(公告)号：US07781830B2

公开(公告)日：2010-08-24

申请号：US12174110

申请日：2008-07-16

申请人： Hsiao Che Wu ,  Ming Yen Li ,  Wen Li Tsai ,  Bin Siang Tsai

发明人： Hsiao Che Wu ,  Ming Yen Li ,  Wen Li Tsai ,  Bin Siang Tsai

IPC分类号： H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/28061 ,  H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

摘要： A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

摘要翻译： 凹陷沟道晶体管包括具有沟槽隔离结构的半导体衬底，在半导体衬底中具有下部块的栅极结构和位于半导体衬底上的上部块，位于上部块的两侧和下部块上方的两个掺杂区域 以及位于上块的侧壁处并且具有夹在上块和掺杂区之间的底端的绝缘垫片。 特别地，两个掺杂区域分别用作源极和漏极区，并且栅极结构的下部块用作凹陷沟道晶体管的凹入栅极。

公开(公告)号：US07759252B2

公开(公告)日：2010-07-20

申请号：US11822754

申请日：2007-07-10

申请人： Yeng-Peng Wang

发明人： Yeng-Peng Wang

IPC分类号： H01L21/302

CPC分类号： H01L21/3081 ,  H01L21/3086 ,  H01L27/10861

摘要： The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of the substrate. Then, the hard masks and the substrate are patterned in sequence to form a plurality of trenches in the substrate. Finally, before performing a wet bath step, the edge of the substrate is backside-etched to remove needle structures on the edge of the substrate.

摘要翻译： 本发明涉及两步背面蚀刻的方法。 首先，提供具有多个硬掩模的基板。 接下来，衬底的背面和边缘被背面蚀刻以去除衬底的背面和边缘上的硬掩模的部分。 然后，顺序地对硬掩模和衬底进行构图，以在衬底中形成多个沟槽。 最后，在进行湿浴步骤之前，对衬底的边缘进行背面蚀刻以去除衬底边缘上的针结构。

公开(公告)号：US20100117050A1

公开(公告)日：2010-05-13

申请号：US12269282

申请日：2008-11-12

申请人： Frederick T. Chen ,  Ming-Jinn Tsai

发明人： Frederick T. Chen ,  Ming-Jinn Tsai

IPC分类号： H01L45/00 ,  H01L21/06

CPC分类号： H01L45/06 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/128 ,  H01L45/14 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1691

摘要： A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers.

摘要翻译： 提供具有电隔离导体的相变存储元件。 相变存储元件包括：第一电极和第二电极; 电连接到第一电极和第二电极的相变材料层; 以及设置在第一电极和第二电极之间的至少两个电隔离导体，直接接触相变材料层。

公开(公告)号：US07678606B2

公开(公告)日：2010-03-16

申请号：US11850019

申请日：2007-09-04

申请人： Frederick T Chen

发明人： Frederick T Chen

IPC分类号： H01L21/06

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

摘要： A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second conductive spacer, wherein the second conductive spacer is electrically connected to the first conductive spacer through the second portion of the phase change layer.

摘要翻译： 公开了一种相变存储器件。 第二导电间隔物位于第一导电间隔物下方。 相变层包括基本上平行于第一和第二导电间隔物的第一部分和位于第二导电间隔物顶部上的第二部分，其中第二导电间隔物通过相变的第二部分电连接到第一导电间隔物 层。

公开(公告)号：US07670869B2

公开(公告)日：2010-03-02

申请号：US11976837

申请日：2007-10-29

申请人： Tu-Hao Yu

发明人： Tu-Hao Yu

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer of the pillar structure. A top electrode electrically connects the second electrode layer of the pillar structure.

摘要翻译： 公开了一种存储器件。 柱结构包括第一电极层，覆盖第一电极层的电介质层和覆盖在电介质层上的第二电极层。 相变层覆盖柱结构的周围。 底部电极电连接柱状结构的第一电极层。 顶电极电连接柱结构的第二电极层。

公开(公告)号：US07655941B2

公开(公告)日：2010-02-02

申请号：US11940563

申请日：2007-11-15

申请人： Yung-Fa Lin ,  Te-Chun Wang

发明人： Yung-Fa Lin ,  Te-Chun Wang

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691 ,  Y10S438/90

摘要： A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers.

摘要翻译： 一种相变存储器件，包括衬底。 彼此隔离的多个底部电极在基板上。 绝缘层与相邻的两个底部电极的表面的一部分交叉。 一对相变材料间隔物位于绝缘层的一对侧壁上，其中一对相变材料间隔物分别位于相邻的两个底部电极之间。 顶部电极位于绝缘层上并覆盖相变材料间隔物。