发明授权
US06876035B2 High voltage N-LDMOS transistors having shallow trench isolation region
失效
具有浅沟槽隔离区的高压N-LDMOS晶体管
- 专利标题: High voltage N-LDMOS transistors having shallow trench isolation region
- 专利标题(中): 具有浅沟槽隔离区的高压N-LDMOS晶体管
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申请号: US10249766申请日: 2003-05-06
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公开(公告)号: US06876035B2公开(公告)日: 2005-04-05
- 发明人: Wagdi W. Abadeer , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti
- 申请人: Wagdi W. Abadeer , Jeffrey S. Brown , Robert J. Gauthier, Jr. , Jed H. Rankin , William R. Tonti
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: McGinn & Gibb, PLLC
- 代理商 Mark F. Chadurjian, Esq.
- 主分类号: H01L21/265
- IPC分类号: H01L21/265 ; H01L21/336 ; H01L29/06 ; H01L29/08 ; H01L29/423 ; H01L29/78 ; H01L29/76 ; H01L23/58
摘要:
A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.