发明授权
US06884673B2 Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor
有权
形成具有金属 - 绝缘体 - 金属(MIM)电容器的集成电路器件的方法
- 专利标题: Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor
- 专利标题(中): 形成具有金属 - 绝缘体 - 金属(MIM)电容器的集成电路器件的方法
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申请号: US10160646申请日: 2002-05-31
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公开(公告)号: US06884673B2公开(公告)日: 2005-04-26
- 发明人: Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
- 申请人: Jae-hyun Joo , Cha-young Yoo , Wan-don Kim , Yong-kuk Jeong
- 申请人地址: KR
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Myers Bigel Sibley & Sajovec
- 优先权: KR10-2001-0030529 20010531
- 主分类号: H01L27/108
- IPC分类号: H01L27/108 ; H01L21/02 ; H01L21/8242
摘要:
In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.
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