公开(公告)号：US20050161727A1

公开(公告)日：2005-07-28

申请号：US11083874

申请日：2005-03-18

申请人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

发明人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L29/76 ,  H01L21/20

CPC分类号： H01L28/60 ,  H01L27/10855 ,  H01L28/91

摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

摘要翻译： 在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。 电介质层位于下电极上，电容器的上电极位于电介质层上。 在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。 接触塞设置在阻挡层上的孔中。 电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。 电介质层位于下电极上，电容器的上电极位于电介质层上。

公开(公告)号：US06884673B2

公开(公告)日：2005-04-26

申请号：US10160646

申请日：2002-05-31

申请人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

发明人： Jae-hyun Joo ,  Cha-young Yoo ,  Wan-don Kim ,  Yong-kuk Jeong

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/60 ,  H01L27/10855 ,  H01L28/91

摘要： In some embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A unitary lower electrode of a capacitor is disposed on the substrate and has a contact plug portion thereof that is disposed in the hole. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer. In other embodiments, an integrated circuit device includes a substrate and an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate. A barrier layer is disposed on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer. A contact plug is disposed in the hole on the barrier layer. A lower electrode of a capacitor is disposed on the contact plug and engages the contact plug at a boundary therebetween. A dielectric layer is on the lower electrode and an upper electrode of the capacitor is on the dielectric layer.

摘要翻译： 在一些实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 电容器的整体下电极设置在基板上，并且具有设置在孔中的接触插塞部分。 电介质层位于下电极上，电容器的上电极位于电介质层上。 在其他实施例中，集成电路器件包括衬底和衬底上的层间绝缘层，其中具有暴露衬底的孔。 阻挡层设置在衬底的暴露部分和层间绝缘层的侧壁上。 接触塞设置在阻挡层上的孔中。 电容器的下电极设置在接触插头上，并在接触插塞之间的边界处接合。 电介质层位于下电极上，电容器的上电极位于电介质层上。

公开(公告)号：US06815221B2

公开(公告)日：2004-11-09

申请号：US10105181

申请日：2002-03-25

申请人： Wan-don Kim ,  Cha-young Yoo ,  Doo-sup Hwang ,  Jae-hyun Joo ,  Eun-ae Chung ,  Yong-kuk Jeong

发明人： Wan-don Kim ,  Cha-young Yoo ,  Doo-sup Hwang ,  Jae-hyun Joo ,  Eun-ae Chung ,  Yong-kuk Jeong

IPC分类号： H01G706

CPC分类号： H01L28/55 ,  H01L28/60 ,  H01L28/91

摘要： A method for manufacturing a capacitor of a semiconductor memory device by controlling thermal budgets is provided. In the method for manufacturing a capacitor of a semiconductor memory device, a lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.

摘要翻译： 提供了一种通过控制热预算来制造半导体存储器件的电容器的方法。 在制造半导体存储器件的电容器的方法中，在半导体衬底上形成下电极。 下电极用第一热预算进行热处理。 在热处理的下电极上形成电介质层。 通过用小于第一热预算的第二热预算对介电层进行热处理来使介质层结晶。

公开(公告)号：US06649502B2

公开(公告)日：2003-11-18

申请号：US09859168

申请日：2001-05-16

申请人： Cha-young Yoo ,  Han-jin Lim ,  Wan-don Kim ,  Se-jin Lee ,  Soon-yeon Park ,  Yong-kuk Jeong ,  Han-mei Choi ,  Gyung-hoon Hong ,  Seok-jun Won

发明人： Cha-young Yoo ,  Han-jin Lim ,  Wan-don Kim ,  Se-jin Lee ,  Soon-yeon Park ,  Yong-kuk Jeong ,  Han-mei Choi ,  Gyung-hoon Hong ,  Seok-jun Won

IPC分类号： H01L213205

CPC分类号： H01L21/02183 ,  C23C16/405 ,  C23C16/45557 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31604 ,  H01L28/40 ,  H01L28/56

摘要： A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C. and a pressure in a range from about 0.1 Torr to about 10.0 Torr during formation of a second tantalum oxide layer.

公开(公告)号：US07008837B2

公开(公告)日：2006-03-07

申请号：US10776053

申请日：2004-02-11

申请人： Seok-jun Won ,  Jung-hee Chung ,  Yong-kuk Jeong ,  Se-hoon Oh ,  Dae-jin Kwon ,  Cha-young Yoo

发明人： Seok-jun Won ,  Jung-hee Chung ,  Yong-kuk Jeong ,  Se-hoon Oh ,  Dae-jin Kwon ,  Cha-young Yoo

IPC分类号： H01L21/8242

CPC分类号： H01L21/02068 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/91

摘要： In a method of manufacturing a capacitor by performing a multi-stepped wet treatment on the surface of a metal electrode, a lower metal electrode of a capacitor is formed, and a primary wet treatment is performed on the surface of the lower metal electrode to remove unwanted surface oxides that may exist on the surface of the lower metal electrode. A secondary wet treatment is then performed on the surface of the lower metal electrode by using a different etchant than the etchant used in the primary wet treatment, in order to remove unwanted surface organic materials that may exist on the surface of the lower metal electrode. A dielectric layer is then formed on the lower metal electrode using a high-k dielectric material. An upper metal electrode is formed on the dielectric layer.

摘要翻译： 在通过对金属电极的表面进行多级湿式处理来制造电容器的方法中，形成电容器的下部金属电极，并对下部金属电极的表面进行一次湿式处理以除去 可能存在于下金属电极表面的不希望的表面氧化物。 然后通过使用与初次湿处理中使用的蚀刻剂不同的蚀刻剂在下金属电极的表面上进行二次湿处理，以便去除可能存在于下金属电极表面上的不希望的表面有机材料。 然后使用高k电介质材料在下金属电极上形成电介质层。 在电介质层上形成上金属电极。

公开(公告)号：US07316961B2

公开(公告)日：2008-01-08

申请号：US11273504

申请日：2005-11-14

申请人： Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong

发明人： Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong

IPC分类号： H01L21/20

CPC分类号： H01L28/65 ,  H01L21/31111 ,  H01L28/55

摘要： Provided is a method of manufacturing a semiconductor device with enhancements of electrical characteristics. The method includes sequentially forming a lower electrode and an insulating layer on a semiconductor substrate, dry-etching a region of the insulating layer corresponding to a capacitor forming region so that the lower electrode is not exposed, forming an inter-insulating layer by wet-etching the insulating layer so that a region of the lower electrode corresponding to the capacitor forming region is exposed, and sequentially forming a dielectric layer and an upper electrode on the capacitor forming region to fabricate a capacitor.

摘要翻译： 提供一种制造具有电特性增强的半导体器件的方法。 该方法包括在半导体衬底上顺序地形成下电极和绝缘层，对与电容器形成区相对应的绝缘层的区域进行干蚀刻，使得下电极不被暴露，通过湿法形成绝缘层， 蚀刻绝缘层，使得与电容器形成区域相对应的下电极的区域被暴露，并且在电容器形成区域上依次形成电介质层和上电极以制造电容器。

公开(公告)号：US20070178644A1

公开(公告)日：2007-08-02

申请号：US11698070

申请日：2007-01-26

申请人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

发明人： Ja-eung Koo ,  Il-young Yoon ,  Jae-ouk Choo ,  Yong-kuk Jeong ,  Seo-woo Nam ,  Hong-jae Shin

IPC分类号： H01L21/336

CPC分类号： H01L21/3212 ,  H01L21/76801 ,  H01L21/7684

摘要： A semiconductor device having a dielectric or an insulating layer with decreased (or minimal) erosion properties when performing metal Chemical Mechanical Polishing (CMP) and a method of fabricating the same are provided. The semiconductor device may include gate electrodes formed on a substrate. A first interlayer oxide layer may be formed on the substrate and between the gate electrodes. A second interlayer oxide layer, which is harder than the first interlayer oxide layer, may be formed on the first interlayer oxide layer. A plug electrode may be formed through the second interlayer oxide layer and the first interlayer oxide layer.

摘要翻译： 提供了当执行金属化学机械抛光（CMP）时具有降低（或最小）腐蚀性能的电介质或绝缘层的半导体器件及其制造方法。 半导体器件可以包括形成在衬底上的栅电极。 第一层间氧化物层可以形成在衬底上和栅电极之间。 可以在第一层间氧化物层上形成比第一层间氧化物层硬的第二层间氧化物层。 可以通过第二层间氧化物层和第一层间氧化物层形成插塞电极。

公开(公告)号：US20060158829A1

公开(公告)日：2006-07-20

申请号：US11335411

申请日：2006-01-19

申请人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

发明人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

IPC分类号： H01G4/20

CPC分类号： H01G4/10 ,  H01G4/20

摘要： Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

公开(公告)号：US07407897B2

公开(公告)日：2008-08-05

申请号：US11173624

申请日：2005-07-01

申请人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L29/00

CPC分类号： H01L28/40 ,  H01L28/65 ,  Y10S438/957

摘要： In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

摘要翻译： 在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。 为了获得这些优点，在​​下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。 下电介质膜和上电介质膜可以由SiO 2组成。 中间电介质膜可以由HFO 2 N 2构成。

公开(公告)号：US20050152094A1

公开(公告)日：2005-07-14

申请号：US11032150

申请日：2005-01-11

申请人： Yong-kuk Jeong ,  Jung-Hyoung Lee ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim ,  Min-woo Song

发明人： Yong-kuk Jeong ,  Jung-Hyoung Lee ,  Seok-Jun Won ,  Dae-Jin Kwon ,  Weon-Hong Kim ,  Min-woo Song

IPC分类号： H01L27/108 ,  H01G4/10 ,  H01G4/20 ,  H01L21/02 ,  H01L27/08 ,  H01G4/28

CPC分类号： H01L21/02172 ,  H01G4/10 ,  H01G4/20 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31645 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/65

摘要： In a capacitor, and a method of fabricating the same, the capacitor includes a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer, wherein the dielectric layer includes a lower dielectric region contacting the lower electrode, an upper dielectric region contacting the upper electrode, and at least one middle dielectric region between the lower dielectric region and the upper dielectric region, the at least one middle dielectric region having a less crystalline region than both the lower dielectric region and the upper dielectric region.

摘要翻译： 在电容器及其制造方法中，电容器包括下电极，下电极上的电介质层和电介质层上的上电极，其中介电层包括与下电极接触的下电介质区域， 与上部电极接触的上部电介质区域，以及位于下部电介质区域和上部电介质区域之间的至少一个中间电介质区域，所述至少一个中间电介质区域具有比下部电介质区域和上部电介质区域更小的结晶区域 。