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发明授权
US06886106B2 System and method for controlling a multiplexer for selecting between an input clock and an input duty-cycle-corrected clock and outputting the selected clock and an enable signal 失效
用于控制多路复用器的系统和方法，用于在输入时钟和输入占空比校正时钟之间选择并输出所选择的时钟和使能信号

System and method for controlling a multiplexer for selecting between an input clock and an input duty-cycle-corrected clock and outputting the selected clock and an enable signal
摘要：
A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
摘要（中）：

一种用于基于整数的值从输入时钟提供动态可变输出时钟的方法和装置，其中整数可以连续地修改。 本发明还提供了采样周期输出，其是具有输入时钟周期的宽度的使能脉冲，其在输入和输出时钟的上升沿对准之前被断言为一个或两个输入时钟周期，其作为上升沿 边缘对齐使能信号，在采样周期断言和上升沿对齐事件之间保持一一对应，而不管整数值的动态变化。

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