Invention Grant
US06895540B2 Mux scan cell with delay circuit for reducing hold-time violations
失效
具有延迟电路的Mux扫描单元，以减少持续时间违规
- Patent Title: Mux scan cell with delay circuit for reducing hold-time violations
- Patent Title (中): 具有延迟电路的Mux扫描单元，以减少持续时间违规
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Application No.: US10064475Application Date: 2002-07-18
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Publication No.: US06895540B2Publication Date: 2005-05-17
- Inventor: Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang
- Applicant: Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Faraday Technology Corp.
- Current Assignee: Faraday Technology Corp.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: G01R31/3185
- IPC: G01R31/3185 ; G01R31/28 ; G06F9/45 ; H01L25/00
Abstract:
A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.
Public/Granted literature
- US20040015759A1 Mux scan cell with delay circuit for reducing hold-time violations Public/Granted day:2004-01-22
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