发明授权
- 专利标题： Semiconductor device having gate electrode of stacked structure including polysilicon layer and metal layer and method of manufacturing the same
- 专利标题（中）： 具有包括多晶硅层和金属层的堆叠结构的栅电极的半导体器件及其制造方法
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申请号： US10654925申请日： 2003-09-05
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公开(公告)号： US06897534B2公开(公告)日： 2005-05-24
- 发明人: Kazuya Ohuchi , Atsushi Azuma
- 申请人： Kazuya Ohuchi , Atsushi Azuma
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Pillsbury Winthrop Shaw Pittman LLP
- 优先权： JP10-286505 19981008
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/28 ; H01L21/318 ; H01L21/336 ; H01L21/60 ; H01L29/76 ; H01L29/94 ; H01L31/062
摘要：
The present invention provides a semiconductor device, comprising a gate electrode of a stacked structure consisting of a polysilicon layer and a metal layer, a cap insulating film formed on the gate electrode, and a gate side wall film formed on the side wall of the gate electrode. The cap insulating film consists of an insulating film containing a silicon oxide-based layer and a silicon nitride layer and serves to protect the upper surface of the gate electrode. Further, the gate side wall film consists of an insulating film containing a silicon nitride film and a silicon oxide film and serves to protect the side surface of the gate electrode.
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