发明授权
US06898683B2 Clock synchronized dynamic memory and clock synchronized integrated circuit
有权
时钟同步动态存储器和时钟同步集成电路
- 专利标题： Clock synchronized dynamic memory and clock synchronized integrated circuit
- 专利标题（中）： 时钟同步动态存储器和时钟同步集成电路
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申请号： US09922742申请日： 2001-08-07
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公开(公告)号： US06898683B2公开(公告)日： 2005-05-24
- 发明人: Toshikazu Nakamura
- 申请人： Toshikazu Nakamura
- 申请人地址： JP Kawasaki
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： JP Kawasaki
- 代理机构： Arent Fox PLLC
- 优先权： JP2000-384669 20001219; JP2000-398894 20001227
- 主分类号： G11C11/4093
- IPC分类号： G11C11/4093 ; G06F13/16 ; G06F13/00
摘要：
A synchronous dynamic memory has a clock input buffer receiving an external clock and outputting an input external clock, a command input buffer receiving commands, an address input buffer receiving addresses, and a data input buffer receiving data. During normal operation mode, the clock input buffer supplies the clock to the command, address, and data input buffers. During data hold modes, such as power down mode, the clock input buffer supplies the clock to the command input buffer but not to the address and data input buffers.
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