发明授权
US06922783B2 Method and apparatus for conserving power on a multiprocessor integrated circuit
失效
在多处理器集成电路上节省功率的方法和装置
- 专利标题： Method and apparatus for conserving power on a multiprocessor integrated circuit
- 专利标题（中）： 在多处理器集成电路上节省功率的方法和装置
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申请号： US10050735申请日： 2002-01-16
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公开(公告)号： US06922783B2公开(公告)日： 2005-07-26
- 发明人: Derek Knee , Samuel Naffziger
- 申请人： Derek Knee , Samuel Naffziger
- 申请人地址： US TX Houston
- 专利权人： Hewlett-Packard Development Company, L.P.
- 当前专利权人： Hewlett-Packard Development Company, L.P.
- 当前专利权人地址： US TX Houston
- 主分类号： G06F12/08
- IPC分类号： G06F12/08 ; G06F1/26 ; G06F1/32 ; G06F15/16 ; G06F15/78 ; H04L9/32
摘要：
A multiple processor integrated circuit has a first processor-first level cache combination powered by a first power terminal, and a second processor-first level cache combination powered by a second power terminal. There is common circuitry coupled to each processor-cache combination. In a particular embodiment, the processor-cache combinations are capable of receiving independently controlled power over the power terminals.
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