发明授权
US06924228B2 Method of forming a via contact structure using a dual damascene technique
有权
使用双镶嵌技术形成通孔接触结构的方法
- 专利标题: Method of forming a via contact structure using a dual damascene technique
- 专利标题(中): 使用双镶嵌技术形成通孔接触结构的方法
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申请号: US10748900申请日: 2003-12-30
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公开(公告)号: US06924228B2公开(公告)日: 2005-08-02
- 发明人: Il-Goo Kim , Sang-Rok Hah
- 申请人: Il-Goo Kim , Sang-Rok Hah
- 申请人地址: KR Suwon-si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si
- 代理机构: F. Chau & Associates, LLC
- 优先权: KR10-2003-0014122 20030306
- 主分类号: H01L21/28
- IPC分类号: H01L21/28 ; H01L21/768 ; H01L21/4763
摘要:
A method of forming a via contact structure using a dual damascene technique is provided. The method includes forming a lower interconnection line on a semiconductor substrate and sequentially forming an inter-metal dielectric layer and a hard mask layer on the semiconductor substrate having the lower interconnection line. The hard mask layer and the inter-metal dielectric layer are successivley patterned to form a via hole that exposes the lower interconnnection line. A sacrificial layer filling the via hole is formed on the hard mask layer. The sacrificial layer and the hard mask layer are patterned to form a first sacrificial layer pattern having an opening that crosses over the via hole and a second sacrificial layer pattern that remains in the via hole and to simultaneously form a hard mask pattern underneath the first sacrificial layer pattern. The inter-metal dielectric layer is partially etched using the hard mask pattern as an etching mask, thereby forming a trench in the inter-metal dielectric layer. The second sacrificial layer pattern is selectively removed to expose the the lower interconnection line.
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