发明授权
- 专利标题: Multilayered integrated circuit with extraneous conductive traces
- 专利标题(中): 多层集成电路与外部导电迹线
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申请号: US10686545申请日: 2003-10-14
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公开(公告)号: US06924552B2公开(公告)日: 2005-08-02
- 发明人: James P. Baukus , Lap-Wai Chow , William M. Clark, Jr. , Paul Ou Yang
- 申请人: James P. Baukus , Lap-Wai Chow , William M. Clark, Jr. , Paul Ou Yang
- 申请人地址: US CA Malibu US CA Santa Clara
- 专利权人: HRL Laboratories, LLC,Promtek
- 当前专利权人: HRL Laboratories, LLC,Promtek
- 当前专利权人地址: US CA Malibu US CA Santa Clara
- 代理机构: Ladas & Parry LLP
- 主分类号: H01L23/04
- IPC分类号: H01L23/04 ; H01L23/48 ; H01L23/52 ; H01L23/522 ; H01L23/528 ; H01L23/58 ; H01L27/02 ; H01L29/40
摘要:
A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.
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