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公开(公告)号：US06924552B2
公开(公告)日：2005-08-02
申请号：US10686545
申请日：2003-10-14
IPC分类号： H01L23/04 , H01L23/48 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/58 , H01L27/02 , H01L29/40
CPC分类号： H01L27/0203 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made of a material which is the same as the material in the conductive layers and have dimensions which are the same as the dimension of the material in the conductive layers. The extraneous conductive lines perform functions which are unnecessary to the operation of the integrated circuit and are undistinguishable from the functional conductive lines, thus burdening the work of a reverse engineer. The method of designing the multilayered circuit comprises a step of providing a computer generated representation of the extraneous conductive lines.
摘要翻译： 提供多层集成电路和设计多层集成电路的方法。 电路包括放置在导电层中的至少两个导电层和外部导电线。 外部导电线由与导电层中的材料相同的材料制成，其尺寸与导电层中材料的尺寸相同。 外部导线执行对集成电路的操作不必要的功能，并且与功能导线不可区分，从而加重了逆向工程师的工作。 设计多层电路的方法包括提供计算机生成的外部导电线的表示的步骤。
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公开(公告)号：US20090170255A1
公开(公告)日：2009-07-02
申请号：US12399628
申请日：2009-03-06
IPC分类号： H01L21/8238
CPC分类号： H01L21/823892 , H01L27/02
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。
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3.发明授权Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact 失效永久性地使用采用双重多晶硅层CMOS工艺的埋入触点实现晶体管公开(公告)号：US06740942B2
公开(公告)日：2004-05-25
申请号：US09882892
申请日：2001-06-15
IPC分类号： H01L2976
CPC分类号： H01L27/0203 , H01L21/76895 , H01L21/823462 , H01L23/576 , H01L27/0883 , H01L29/7834 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.
摘要翻译： 永久导通MOS晶体管包括在第二导电类型的硅阱区域中的第一导电类型的硅源极和漏极区域。 所述第一导电类型的硅接触区域埋在所述阱区域中，所述接触区域接触所述源极区域和所述漏极区域。 选择性地将第一栅极绝缘层放置在硅源极和漏极区域上。 第二栅极绝缘层选择性地放置在第一栅极绝缘层上方和硅接触区域上。 多晶硅栅极区域放置在第二栅极绝缘层上。
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4.发明授权Conductive channel pseudo block process and circuit to inhibit reverse engineering 失效导电通道伪块处理和电路抑制反向工程公开(公告)号：US08258583B1
公开(公告)日：2012-09-04
申请号：US12949657
申请日：2010-11-18
IPC分类号： H01L27/088
CPC分类号： H01L27/0203 , G06K19/073 , G06K19/07363 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。
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5.发明授权Conductive channel pseudo block process and circuit to inhibit reverse engineering 有权导电通道伪块处理和电路抑制逆向工程公开(公告)号：US07888213B2
公开(公告)日：2011-02-15
申请号：US11375846
申请日：2006-03-14
IPC分类号： H01L21/8236
CPC分类号： H01L27/0203 , G06K19/073 , G06K19/07363 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。
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公开(公告)号：US07514755B2
公开(公告)日：2009-04-07
申请号：US10735841
申请日：2003-12-12
IPC分类号： H01L29/76
CPC分类号： H01L21/823892 , H01L27/02
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。
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公开(公告)号：US07008873B2
公开(公告)日：2006-03-07
申请号：US11089415
申请日：2005-03-23
IPC分类号： H01L21/44 , H01L21/00 , H01L21/84 , H01L21/338 , H01L21/4763
CPC分类号： H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.
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8.发明授权Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations 失效防止逆向工程的集成电路和使用无金属端接的通孔制造相同工艺的方法公开(公告)号：US06791191B2
公开(公告)日：2004-09-14
申请号：US09768911
申请日：2001-01-24
IPC分类号： H01L2348
CPC分类号： H01L23/573 , H01L23/5226 , H01L27/0203 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A device adapted to protect integrated circuits from reverse engineering comprising a part looking like a via connecting two metal layers, but in fact attached only to one metal layer and spaced from the other. Having such “trick” via would force a reverse engineer to think there is a connection where there is none. A method for fabricating such device.
摘要翻译： 一种适用于保护集成电路免受反向工程的设备，包括看起来像连接两个金属层的通孔的部分，但实际上仅附接到一个金属层并与另一个间隔开。 通过这样的“诡计”将迫使反向工程师认为没有连接。 一种制造这种装置的方法。
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9.发明授权
公开(公告)号：US5866933A
公开(公告)日：1999-02-02
申请号：US191063
申请日：1994-02-03
IPC分类号： H01L23/52 , G11C7/24 , H01L21/3205 , H01L21/822 , H01L23/58 , H01L27/02 , H01L27/04 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002
摘要： An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.
摘要翻译： 通过将类似导电性的掺杂电路元件与衬底中的掺杂注入相连而不是金属化互连来保护集成电路免于逆向工程。 掺杂电路元件及其对应的注入互连可以在具有公共注入掩模的公共制造步骤中形成，使得它们具有类似掺杂剂浓度的整体结构。 衬底表面之上的金属化可被设计成提供互连的进一步屏蔽，并且微桥可以被添加到在互连路径中跨越晶体管栅极材料的条带。
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公开(公告)号：US07344932B2
公开(公告)日：2008-03-18
申请号：US11208470
申请日：2005-08-18
IPC分类号： H01L21/338
CPC分类号： H01L23/573 , H01L27/02 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
摘要翻译： 用于伪装集成电路结构的技术和结构。 设置具有受控轮廓的导电材料层，以便当实际上该装置不可操作时，提供类似于可操作装置的导电材料的假象边缘。
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