发明授权
- 专利标题: Semiconductor memory device having test mode
- 专利标题(中): 具有测试模式的半导体存储器件
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申请号: US10442974申请日: 2003-05-22
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公开(公告)号: US06930938B2公开(公告)日: 2005-08-16
- 发明人: Kenichi Yasuda
- 申请人: Kenichi Yasuda
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: McDermott Will & Emery LLP
- 优先权: JP2002-345255 20021128
- 主分类号: G01R31/30
- IPC分类号: G01R31/30 ; G01R31/28 ; G11C11/401 ; G11C29/02 ; G11C29/06 ; G11C29/00
摘要:
In a burn-in test, a sense amplifier circuit is separated from each bit line by a bit line separation switch. In this state, a bit line switch circuit connects one of complementary bit lines to a first voltage node, and connects the other complementary bit line to a second voltage node in blocks on both sides. A first bit line voltage supplied by the first voltage node and a second bit line voltage supplied by the second voltage node can be set independently of each other at least in the burn-in test.
公开/授权文献
- US20040105334A1 Semiconductor memory device having test mode 公开/授权日:2004-06-03
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