发明授权
- 专利标题: Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise
- 专利标题(中): 优化时钟分配的方法和装置,以减少电源噪声的影响
-
申请号: US10021058申请日: 2001-12-19
-
公开(公告)号: US06934872B2公开(公告)日: 2005-08-23
- 发明人: Keng L. Wong , Hung-Piao Ma , Tawfik M. Rahal-Arabi , Javed Barkatullah , Edward A. Burton
- 申请人: Keng L. Wong , Hung-Piao Ma , Tawfik M. Rahal-Arabi , Javed Barkatullah , Edward A. Burton
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F1/10
- IPC分类号: G06F1/10 ; G06F1/04 ; G06F17/50
摘要:
A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.