中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.01 seconds)

    PLL with controlled VCO bias
    1.
    发明申请
    PLL with controlled VCO bias 有权
    具有受控VCO偏置的PLL

    公开(公告)号：US20070046343A1

    公开(公告)日：2007-03-01

    申请号：US11218207

    申请日：2005-08-31

    Applicant: Nasser Kurd ,  Javed Barkatullah

    Inventor： Nasser Kurd ,  Javed Barkatullah

    IPC: H03L7/06

    CPC classification number: H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00045 ,  H03K2005/00208 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/18

    Abstract: In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a sufficient level if it is insufficient. Other embodiments may be disclosed herein.

    Abstract translation: 在一些实施例中，提供具有输出以提供目标频率的PLL输出时钟的PLL。 PLL包括VCO以产生要用于产生PLL输出时钟的时钟。 还提供了如果不足够将VCO的偏置电平维持在足够的电平的电路。 本文可以公开其它实施例。

    Adaptive frequency clock generation system
    3.
    发明申请
    Adaptive frequency clock generation system 失效
    自适应频率时钟发生系统

    公开(公告)号：US20050218955A1

    公开(公告)日：2005-10-06

    申请号：US10813551

    申请日：2004-03-31

    Applicant: Nasser Kurd ,  Javed Barkatullah ,  Paul Madland

    Inventor： Nasser Kurd ,  Javed Barkatullah ,  Paul Madland

    IPC: H03B5/00 ,  H03L7/093 ,  H03L7/22

    CPC classification number: H03L7/093 ,  H03L7/22

    Abstract: A clock generating apparatus is provided that includes a first phase lock loop device powered by an analog (or fixed) power supply voltage and a second phase lock loop device powered by the analog power supply voltage and a digital power supply voltage. The second phase lock loop device to output a clock signal having an adaptive frequency based on the digital power supply voltage.

    Abstract translation: 提供了一种时钟发生装置，其包括由模拟（或固定）电源电压供电的第一锁相环装置和由模拟电源电压和数字电源电压供电的第二锁相环装置。 第二锁相环装置，用于基于数字电源电压输出具有自适应频率的时钟信号。

    Method and apparatus for power consumption reduction
    5.
    发明申请
    Method and apparatus for power consumption reduction 失效
    降低功耗的方法和装置

    公开(公告)号：US20060259890A1

    公开(公告)日：2006-11-16

    申请号：US11486030

    申请日：2006-07-14

    Applicant: James Tschanz ,  Nasser Kurd ,  Javed Barkatullah ,  Vivek De

    Inventor： James Tschanz ,  Nasser Kurd ,  Javed Barkatullah ,  Vivek De

    IPC: G06F17/50

    CPC classification number: G06F17/5045

    Abstract: A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

    Abstract translation: 提供了一种降低功耗的方法和芯片设计。 具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。 具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。 第二功能块内的边沿触发电路可以用双边沿触发电路代替。 相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。

    Method for power consumption reduction
    6.
    发明授权
    Method for power consumption reduction 有权
    降低功耗的方法

    公开(公告)号：US07096433B2

    公开(公告)日：2006-08-22

    申请号：US10703562

    申请日：2003-11-10

    Applicant: James W. Tschanz ,  Nasser A. Kurd ,  Javed Barkatullah ,  Vivek K. De

    Inventor： James W. Tschanz ,  Nasser A. Kurd ,  Javed Barkatullah ,  Vivek K. De

    IPC: G06F17/50

    CPC classification number: G06F17/5045

    Abstract: A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

    Abstract translation: 提供了一种降低功耗的方法和芯片设计。 具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。 具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。 第二功能块内的边沿触发电路可以用双边沿触发电路代替。 相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。

    Digital clock skew detection and phase alignment
    7.
    发明授权
    Digital clock skew detection and phase alignment 有权
    数字时钟偏移检测和相位对准

    公开(公告)号：US06622255B1

    公开(公告)日：2003-09-16

    申请号：US09660808

    申请日：2000-09-13

    Applicant: Nasser A. Kurd ,  Javed Barkatullah

    Inventor： Nasser A. Kurd ,  Javed Barkatullah

    IPC: G06F112

    CPC classification number: H03D13/003 ,  G06F1/10 ,  H03K5/133 ,  H03K5/15013 ,  H03L7/07 ,  H03L7/081 ,  H03L7/0814 ,  H03L7/089

    Abstract: A skew measure circuit, an exclusion circuit, and an up/down counter are connected to form a skew detection circuit. The skew measure circuit asserts a first output signal if a first input clock leads a second input clock, and asserts a second output signal if the second clock leads the first clock. The exclusion circuit provides first and second digital pulse signals that represent the outputs of the skew measure circuit. The exclusion circuit also prevents the states of these pulse signals from changing, so long as the skew measure circuit is experiencing metastability. The up/down counter's count is incremented in response to the first pulse signal and decremented in response to the other pulse signal.

    Abstract translation: 连接偏斜测量电路，排除电路和升降计数器以形成偏斜检测电路。 如果第一输入时钟引导第二输入时钟，则偏斜测量电路确定第一输出信号，并且如果第二时钟引导第一时钟，则断言第二输出信号。 排除电路提供表示偏斜测量电路的输出的第一和第二数字脉冲信号。 只要偏差测量电路正在经历亚稳态，排除电路也可以防止这些脉冲信号的状态改变。 升/减计数器的计数响应于第一脉冲信号而增加，并响应于另一个脉冲信号递减。

    Apparatus for power consumption reduction
    8.
    发明授权
    Apparatus for power consumption reduction 失效
    降低功耗的设备

    公开(公告)号：US07562316B2

    公开(公告)日：2009-07-14

    申请号：US11486030

    申请日：2006-07-14

    Applicant: James W. Tschanz ,  Nasser A. Kurd ,  Javed Barkatullah ,  Vivek K. De

    Inventor： James W. Tschanz ,  Nasser A. Kurd ,  Javed Barkatullah ,  Vivek K. De

    IPC: G06F17/50

    CPC classification number: G06F17/5045

    Abstract: A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.

    Abstract translation: 提供了一种降低功耗的方法和芯片设计。 具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。 具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。 第二功能块内的边沿触发电路可以用双边沿触发电路代替。 相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。

    Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise
    10.
    发明授权
    Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise 失效
    优化时钟分配的方法和装置，以减少电源噪声的影响

    公开(公告)号：US06934872B2

    公开(公告)日：2005-08-23

    申请号：US10021058

    申请日：2001-12-19

    Applicant: Keng L. Wong ,  Hung-Piao Ma ,  Tawfik M. Rahal-Arabi ,  Javed Barkatullah ,  Edward A. Burton

    Inventor： Keng L. Wong ,  Hung-Piao Ma ,  Tawfik M. Rahal-Arabi ,  Javed Barkatullah ,  Edward A. Burton

    IPC: G06F1/10 ,  G06F1/04 ,  G06F17/50

    CPC classification number: G06F1/10

    Abstract: A method and apparatus for optimizing clock distribution in a circuit to reduce the effect of power supply noise. Parameters are determined including: a response curve of a power source for a circuit, a delay sensitivity of a clock net in the circuit to the power source, a delay sensitivity of a data net in the circuit to the power source, a data delay for the data net, and a clock delay for the clock net. The clock delay is adjusted to reduce the effect of power supply noise on the data net. The adjusting is based on the response curve of the power source, the delay sensitivity of the clock net, the delay sensitivity of the data net, the data delay, and the clock delay. The adjusting includes adding a pre-distribution clock delay.

    Abstract translation: 一种用于优化电路中的时钟分布以减少电源噪声的影响的方法和装置。 确定参数，包括：电路的电源的响应曲线，到电源的电路中的时钟网络的延迟灵敏度，电路中的数据网到电源的延迟灵敏度，数据延迟 数据网和时钟网的时钟延迟。 调整时钟延迟以减少电源噪声对数据网的影响。 调整是基于电源的响应曲线，时钟网络的延迟灵敏度，数据网络的延迟灵敏度，数据延迟和时钟延迟。 调整包括添加预分配时钟延迟。

Patent Agency Ranking