Invention Grant
US06947806B2 System and method for effective yield loss analysis for semiconductor wafers
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用于半导体晶片的有效屈服损失分析的系统和方法
- Patent Title: System and method for effective yield loss analysis for semiconductor wafers
- Patent Title (中): 用于半导体晶片的有效屈服损失分析的系统和方法
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Application No.: US10655850Application Date: 2003-09-04
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Publication No.: US06947806B2Publication Date: 2005-09-20
- Inventor: Wun Wang
- Applicant: Wun Wang
- Applicant Address: TW Hsinchu
- Assignee: ProMOS Technologies Inc.
- Current Assignee: ProMOS Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: J. C. Patents
- Main IPC: G05B23/02
- IPC: G05B23/02 ; G06F19/00

Abstract:
This invention relates to a method for yield loss analysis of process steps of semiconductor wafers having a plurality of dies, and more particularly relates to a defect inspection technique to determine a hit ratio, computation of yield impact contributions for the defects, and determination of a kill ratio for a specific type of defect. Yield loss is estimated ultimately upon a choice of a defect density distribution function. A defect calibrated factor and a yield impact calibrated factor are introduced herein.
Public/Granted literature
- US20050055121A1 System and methed for effective field loss analysis for semiconductor wafers Public/Granted day:2005-03-10
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