发明授权
- 专利标题： In-plane on-chip decoupling capacitors and method for making same
- 专利标题（中）： 面内片上去耦电容及其制作方法
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申请号： US10890716申请日： 2004-07-13
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公开(公告)号： US06949831B2公开(公告)日： 2005-09-27
- 发明人: Chien Chiang , David B. Fraser
- 申请人： Chien Chiang , David B. Fraser
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763 ; H01L21/768 ; H01L23/48 ; H01L23/522 ; H01L23/528 ; H01L23/58
摘要：
An interconnect structure for microelectronic devices indudes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first Intralayer dielectric of a first dielectric constant therebetween, and a second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween. By providing in-plane selectability of dielectric constant, in-plane decoupling capacitance, as between power supply nodes, can be increased, while in-plane parasitic capacitance between signal lines can be reduced.
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