Invention Grant
- Patent Title: Gate-clocked domino circuits with reduced leakage current
- Patent Title (中): 具有降低漏电流的门控多米诺骨牌电路
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Application No.: US10324307Application Date: 2002-12-18
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Publication No.: US06952118B2Publication Date: 2005-10-04
- Inventor: Shahram Jamshidi , Sudarshan Kumar
- Applicant: Shahram Jamshidi , Sudarshan Kumar
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Jeffrey B. Huter
- Main IPC: H03K19/096
- IPC: H03K19/096
Abstract:
A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.
Public/Granted literature
- US20040119503A1 Gate-clocked domino circuits with reduced leakage current Public/Granted day:2004-06-24
Information query
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