发明授权
- 专利标题： Mask pattern generating method and manufacturing method of semiconductor apparatus
- 专利标题（中）： 半导体装置的掩模图案生成方法和制造方法
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申请号： US10255832申请日： 2002-09-27
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公开(公告)号： US06964031B2公开(公告)日： 2005-11-08
- 发明人: Toshiya Kotani , Satoshi Tanaka , Soichi Inoue , Sachiko Kobayashi , Hirotaka Ichiakwa
- 申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue , Sachiko Kobayashi , Hirotaka Ichiakwa
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权： JP2001-375025 20010929; JP2002-271546 20020918
- 主分类号： H01L21/027
- IPC分类号： H01L21/027 ; G03F1/00 ; G03F1/36 ; G06F17/50 ; H01L21/00
摘要：
A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.
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