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    Mask pattern generating method and manufacturing method of semiconductor apparatus
    1.
    发明授权
    Mask pattern generating method and manufacturing method of semiconductor apparatus 失效
    半导体装置的掩模图案生成方法和制造方法

    公开(公告)号：US06964031B2

    公开(公告)日：2005-11-08

    申请号：US10255832

    申请日：2002-09-27

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue ,  Sachiko Kobayashi ,  Hirotaka Ichiakwa

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue ,  Sachiko Kobayashi ,  Hirotaka Ichiakwa

    IPC分类号： H01L21/027 ,  G03F1/00 ,  G03F1/36 ,  G06F17/50 ,  H01L21/00

    CPC分类号： G03F1/36

    摘要： A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.

    摘要翻译： 一种从设计图案生成掩模图案的掩模图案生成方法，包括准备设计图案，准备校正参数，准备第一校正库，其中多对边缘坐标组和校正值组校正第 登记边缘坐标组，获取所设计图案的边缘坐标组，生成第二校正库，其中在所述第一校正中仅登记与获取的边缘坐标组和校正值组一致的边缘坐标组的多对对 库和模拟，并使用第二校正库校正设计的模式。

    Method for making a design layout and mask
    3.
    再颁专利
    Method for making a design layout and mask 有权
    制作设计布局和面具的方法

    公开(公告)号：USRE42302E1

    公开(公告)日：2011-04-19

    申请号：US11905862

    申请日：2007-10-04

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

    CPC分类号： G06F17/5081

    摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

    摘要翻译： 提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案 所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则 预定条件。

    Method of setting process parameter and method of setting process parameter and/or design rule
    6.
    发明授权
    Method of setting process parameter and method of setting process parameter and/or design rule 有权
    设置过程参数的方法和设置过程参数和/或设计规则的方法

    公开(公告)号：US07120882B2

    公开(公告)日：2006-10-10

    申请号：US11105431

    申请日：2005-04-14

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Koji Hashimoto ,  Soichi Inoue ,  Ichiro Mori

    IPC分类号： G06F17/50

    CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.

    摘要翻译： 公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案 ，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值 判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

    Method of manufacturing a photo mask and method of manufacturing a semiconductor device
    7.
    发明授权
    Method of manufacturing a photo mask and method of manufacturing a semiconductor device 有权
    制造光掩模的方法和制造半导体器件的方法

    公开(公告)号：US07090949B2

    公开(公告)日：2006-08-15

    申请号：US10724738

    申请日：2003-12-02

    申请人： Shigeki Nojima ,  Shoji Mimotogi ,  Satoshi Tanaka ,  Toshiya Kotani ,  Shigeru Hasebe ,  Koji Hashimoto ,  Soichi Inoue ,  Osamu Ikenaga

    发明人： Shigeki Nojima ,  Shoji Mimotogi ,  Satoshi Tanaka ,  Toshiya Kotani ,  Shigeru Hasebe ,  Koji Hashimoto ,  Soichi Inoue ,  Osamu Ikenaga

    IPC分类号： G01F9/00

    CPC分类号： G03F1/36 ,  G03F1/68

    摘要： Disclosed is a method of manufacturing a photo mask comprising preparing mask data for a mask pattern to be formed on a mask substrate, calculating edge moving sensitivity with respect to each of patterns included in the mask pattern using the mask data, the edge moving sensitivity corresponding to a difference between a proper exposure dose and an exposure dose to be set when a pattern edge varies, determining a monitor portion of the mask pattern, based on the calculated edge moving sensitivity, actually forming the mask pattern on the mask substrate, acquiring a dimension of a pattern included in that portion of the mask pattern formed on the mask substrate which corresponds to the monitor portion, determining evaluation value for the mask pattern formed on the mask substrate, based on the acquired dimension, and determining whether the evaluation value satisfies predetermined conditions.

    摘要翻译： 公开了一种制造光掩模的方法，其包括：对掩模基板上形成的掩模图案准备掩模数据，使用掩模数据计算相对于包含在掩模图案中的每个图案的边缘移动灵敏度，边缘移动灵敏度对应 对于在图案边缘变化时要设置的适当曝光剂量和曝光剂量之间的差异，基于计算出的边缘移动灵敏度确定掩模图案的监视部分，实际在掩模基板上形成掩模图案，获取 基于所获取的尺寸，确定在掩模基板上形成的掩模图案的评估值，并且确定评估值是否满足的掩模图案的形成在掩模基板上的对应于监视部分的掩模图案的部分中的图案的尺寸 预定条件。

    Pattern formation method, mask for exposure used for pattern formation, and method of manufacturing the same
    9.
    发明授权
    Pattern formation method, mask for exposure used for pattern formation, and method of manufacturing the same 有权
    图案形成方法，用于图案形成的曝光用掩模及其制造方法

    公开(公告)号：US06727028B2

    公开(公告)日：2004-04-27

    申请号：US10132197

    申请日：2002-04-26

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    IPC分类号： G03F900

    CPC分类号： G03F1/36 ,  G03F7/70433 ,  G03F7/70441

    摘要： In a pattern forming method, a cell pattern of each of memory cells is separated into a first pattern group provided at a predetermined position inside from an endmost portion of a cell and a second pattern group excluding the first pattern group. A mask size of the second pattern group is determined such that the second pattern group secures a sufficient process margin relative to a given size and size accuracy. A mask size of the first pattern group is optimized according to a peripheral pattern environment such that the first pattern group has a desired size under the above condition. A mask pattern of the memory cell is formed according to the mask size of the second pattern group and the first pattern group. The cell pattern is formed on a semiconductor wafer, using the mask pattern.

    摘要翻译： 在图案形成方法中，每个存储单元的单元图案被分离成设置在从单元的最末端部分的内部的预定位置处的第一图案组和除了第一图案组之外的第二图案组。 确定第二图案组的掩模尺寸，使得第二图案组相对于给定的尺寸和尺寸精度确保足够的加工余量。 根据周边图案环境优化第一图案组的掩模尺寸，使得第一图案组在上述条件下具有期望的尺寸。 根据第二图案组和第一图案组的掩模尺寸形成存储单元的掩模图案。 使用掩模图案在半导体晶片上形成电池图案。

    Semiconductor integrated circuit designing method and system
    10.
    发明授权
    Semiconductor integrated circuit designing method and system 有权

    公开(公告)号：US06507931B2

    公开(公告)日：2003-01-14

    申请号：US09892572

    申请日：2001-06-28

    申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Soichi Inoue

    IPC分类号： G06F1750

    CPC分类号： G06F17/5081

    摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.