- Patent Title: Method for in-line testing of flip-chip semiconductor assemblies
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Application No.: US10721110Application Date: 2003-11-24
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Publication No.: US06967113B2Publication Date: 2005-11-22
- Inventor: Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
- Applicant: Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt, PC
- Main IPC: G01R1/04
- IPC: G01R1/04 ; G01R31/26

Abstract:
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
Public/Granted literature
- US20040104741A1 Method for in-line testing of flip-chip semiconductor assemblies Public/Granted day:2004-06-03
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