Method for packaging flip-chip semiconductor assemblies
    1.
    发明授权
    Method for packaging flip-chip semiconductor assemblies 失效
    封装倒装芯片半导体组件的方法

    公开(公告)号:US07074648B2

    公开(公告)日:2006-07-11

    申请号:US10714188

    申请日:2003-11-14

    IPC分类号: H01L21/44 H01L21/48 H01L21/50

    摘要: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    摘要翻译: 每个包括集成电路(IC)裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附着站的探针进行电测试。 在通过将集成电路(IC)芯片压在基板上的互连点以进行电连接的环氧树脂固化之前,可以测试使用“湿”快速固化环氧树脂进行芯片附接的那些组件,而使用“干”环氧树脂的那些组件 在测试之前进行治愈。 在任一种情况下,骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定,并且消除了在维修期间使用已知好模具(KGD)返工程序的需要。

    Method for in-line testing of flip-chip semiconductor assemblies

    公开(公告)号:US06472901B2

    公开(公告)日:2002-10-29

    申请号:US09944507

    申请日:2001-08-30

    IPC分类号: G01R3126

    摘要: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.

    Method for in-line testing of flip-chip semiconductor assemblies
    4.
    发明授权
    Method for in-line testing of flip-chip semiconductor assemblies 失效
    倒装芯片半导体组件的在线测试方法

    公开(公告)号:US06329832B1

    公开(公告)日:2001-12-11

    申请号:US09166369

    申请日:1998-10-05

    IPC分类号: G01R3126

    摘要: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    摘要翻译: 每个包括集成电路(IC)裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附接站的探针进行电测试。 在通过将集成电路(IC)芯片压在基板上的互连点进行电连接而使环氧树脂固化之前,可以测试使用“湿”快速固化环氧树脂进行芯片附着的那些组件,而使用“干”环氧树脂 可以在测试之前治愈。 在任一种情况下,骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定,并且消除了在维修期间使用已知好模具(KGD)返工程序的需要。

    Method for in-line testing of flip-chip semiconductor assemblies

    公开(公告)号:US07105366B2

    公开(公告)日:2006-09-12

    申请号:US10338522

    申请日:2005-09-08

    IPC分类号: G01R31/26

    摘要: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    Method for in-line testing of flip-chip semiconductor assemblies

    公开(公告)号:US07005878B2

    公开(公告)日:2006-02-28

    申请号:US10900610

    申请日:2004-07-27

    IPC分类号: G01R31/26

    摘要: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    Method for in-line testing of flip-chip semiconductor assemblies
    7.
    发明授权
    Method for in-line testing of flip-chip semiconductor assemblies 失效
    倒装芯片半导体组件的在线测试方法

    公开(公告)号:US06369602B1

    公开(公告)日:2002-04-09

    申请号:US09645902

    申请日:2000-08-25

    IPC分类号: G01R3126

    摘要: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    摘要翻译: 每个包括集成电路(IC)裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附接站的探针进行电测试。 在通过将集成电路(IC)芯片压在基板上的互连点进行电连接而使环氧树脂固化之前,可以测试使用“湿”快速固化环氧树脂进行芯片附着的那些组件,而使用“干”环氧树脂 可以在测试之前治愈。 在任一种情况下,骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定,并且消除了在维修期间使用已知好模具(KGD)返工程序的需要。

    Method for in-line testing of flip-chip semiconductor assemblies
    8.
    发明授权
    Method for in-line testing of flip-chip semiconductor assemblies 失效
    倒装芯片半导体组件的在线测试方法

    公开(公告)号:US06982177B2

    公开(公告)日:2006-01-03

    申请号:US10900776

    申请日:2004-07-27

    IPC分类号: G01R31/26

    摘要: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    摘要翻译: 每个包括集成电路(IC)裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附着站的探针进行电测试。 在通过将集成电路(IC)芯片压在基板上的互连点以进行电连接的环氧树脂固化之前,可以测试使用“湿”快速固化环氧树脂进行芯片附接的那些组件,而使用“干”环氧树脂的那些组件 在测试之前进行治愈。 在任一种情况下,骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定,并且消除了在维修期间使用已知好模具(KGD)返工程序的需要。

    Method for in-line testing of flip-chip semiconductor assemblies
    9.
    发明授权
    Method for in-line testing of flip-chip semiconductor assemblies 失效
    倒装芯片半导体组件的在线测试方法

    公开(公告)号:US06962826B2

    公开(公告)日:2005-11-08

    申请号:US10900771

    申请日:2004-07-27

    IPC分类号: G01R1/04 H01L21/66

    摘要: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    摘要翻译: 每个包括集成电路(IC)裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附着站的探针进行电测试。 在通过将集成电路(IC)芯片压在基板上的互连点以进行电连接的环氧树脂固化之前,可以测试使用“湿”快速固化环氧树脂进行芯片附接的那些组件,而使用“干”环氧树脂的那些组件 在测试之前进行治愈。 在任一种情况下,骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定,并且消除了在维修期间使用已知好模具(KGD)返工程序的需要。