发明授权
US06969649B2 Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices
失效
具有具有降低的位线杂散容量的存储器件的半导体集成电路器件的制造方法以及这种半导体集成电路器件
- 专利标题: Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices
- 专利标题(中): 具有具有降低的位线杂散容量的存储器件的半导体集成电路器件的制造方法以及这种半导体集成电路器件
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申请号: US10810884申请日: 2004-03-29
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公开(公告)号: US06969649B2公开(公告)日: 2005-11-29
- 发明人: Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Hideo Aoki , Toshikazu Kumai , Kazuhiko Saito , Michio Nishimura , Michio Tanaka , Katsuo Yuhara , Shinya Nishio , Toshiyuki Kaeriyama , Songsu Cho
- 申请人: Toshihiro Sekiguchi , Yoshitaka Tadaki , Keizo Kawakita , Hideo Aoki , Toshikazu Kumai , Kazuhiko Saito , Michio Nishimura , Michio Tanaka , Katsuo Yuhara , Shinya Nishio , Toshiyuki Kaeriyama , Songsu Cho
- 申请人地址: JP Tokyo US TX Dallas
- 专利权人: Hitachi, Ltd.,Texas Instruments Incorporated
- 当前专利权人: Hitachi, Ltd.,Texas Instruments Incorporated
- 当前专利权人地址: JP Tokyo US TX Dallas
- 代理机构: Antonelli, Terry, Stout and Kraus, LLP.
- 优先权: JP08-135534 19960529
- 主分类号: H01L21/8242
- IPC分类号: H01L21/8242 ; H01L21/60 ; H01L27/108
摘要:
A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.
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