A data output control circuit for use in a synchronous semiconductor memory device, which has a plurality of CAS latency modes, includes a signal generating unit for generating an internal signal corresponding to an input command; a CAS latency mode control unit for outputting the internal signal as a controlled internal signal; a signal shifting unit for generating a plurality of shifted signals by synchronizing the controlled internal signal with a DLL clock signal; and a data output enable signal generating unit for outputting one of the plurality of shifted signals as a data output enable signal depending on a plurality of control signals, wherein each of the plurality of control signals corresponds to two or more continuous CAS latency modes.