公开(公告)号：US07312647B2

公开(公告)日：2007-12-25

申请号：US11623927

申请日：2007-01-17

申请人： Young Bae Choi ,  Kwang Jin Na

发明人： Young Bae Choi ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/151

摘要： A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

公开(公告)号：US20060011298A1

公开(公告)日：2006-01-19

申请号：US11177890

申请日：2005-07-08

申请人： Ji-Eun Lim ,  Byoung-Jae Bae ,  Young-Bae Choi

发明人： Ji-Eun Lim ,  Byoung-Jae Bae ,  Young-Bae Choi

IPC分类号： C23F1/00 ,  C23C16/00

CPC分类号： C23C16/45514 ,  C23C16/45565 ,  C23C16/45574

摘要： Showerheads for use in an apparatus for manufacturing a semiconductor substrate include an injection plate defining a bottom face of a gas receiving space in the showerhead and a gas receiving channel extending within the injection plate. A plurality of exhausting holes in the injection plate are coupled to the gas receiving channel. The exhausting holes are configured to exhaust gas from the gas receiving channel to the bottom face of the gas receiving space. A plurality of channels extend through the injection plate from the bottom face of the gas receiving space configured to flow gas from the bottom face of the gas receiving space out of the space.

摘要翻译： 用于制造半导体衬底的装置的喷头包括限定喷淋头中的气体接收空间的底面的注射板和在注射板内延伸的气体接收通道。 喷射板中的多个排气孔联接到气体接收通道。 排气孔被构造成将气体从气体接收通道排出到气体接收空间的底面。 多个通道从气体容纳空间的底面延伸穿过注射板，该气体接收空间配置成使气体从气体接收空间的底面流出空间。

公开(公告)号：US06977848B2

公开(公告)日：2005-12-20

申请号：US10874326

申请日：2004-06-24

申请人： Young-Bae Choi

发明人： Young-Bae Choi

IPC分类号： G11C11/40 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C7/1051 ,  G11C7/103 ,  G11C7/106 ,  G11C7/1066

摘要： A data output control circuit for use in a synchronous semiconductor memory device, which has a plurality of CAS latency modes, includes a signal generating unit for generating an internal signal corresponding to an input command; a CAS latency mode control unit for outputting the internal signal as a controlled internal signal; a signal shifting unit for generating a plurality of shifted signals by synchronizing the controlled internal signal with a DLL clock signal; and a data output enable signal generating unit for outputting one of the plurality of shifted signals as a data output enable signal depending on a plurality of control signals, wherein each of the plurality of control signals corresponds to two or more continuous CAS latency modes.

公开(公告)号：US20050183826A1

公开(公告)日：2005-08-25

申请号：US11060525

申请日：2005-02-17

申请人： Young-Bae Choi ,  Moon-Sook Lee ,  Byoung-Jae Bae

发明人： Young-Bae Choi ,  Moon-Sook Lee ,  Byoung-Jae Bae

IPC分类号： H01L21/20 ,  C23F1/00 ,  H01J37/32

CPC分类号： H01J37/32522 ,  H01J37/3244

摘要： Showerheads including a plate having a plurality of gas outlet holes extending therethrough and a head cover coupled to the plate to form a space between the plate and the head cover. A gas supply inlet member is configured to provide gas to the space directed toward the head cover. A gas distribution member on an inner face of the head cover facing the space is configured to partially suppress flow of the gas provided to the space in a direction along the gas distribution member to substantially uniformly distribute the gas in the space. The direction along the gas distribution member may be a horizontal direction and the gas provided to the space is directed in a substantially vertical upward direction. Apparatus and methods using the showerheads are also provided.

摘要翻译： 喷头包括具有延伸穿过其中的多个气体出口孔的板，以及联接到该板的头罩，以在板和头盖之间形成空间。 气体供给入口构件被配置为向指向头罩的空间提供气体。 在头盖的面对空间的内表面上的气体分配构件被构造成部分地抑制沿着气体分配构件的方向设置到空间的气体的流动，以将气体基本均匀地分布在空间中。 沿着气体分配构件的方向可以是水平方向，并且设置到空间的气体被引向基本垂直的向上的方向。 还提供了使用喷头的装置和方法。

公开(公告)号：US5937016A

公开(公告)日：1999-08-10

申请号：US916204

申请日：1997-08-22

申请人： Young-Bae Choi

发明人： Young-Bae Choi

IPC分类号： H04L27/22 ,  H03M13/23 ,  H03M13/33 ,  H04L1/00 ,  H04L7/00 ,  H03D1/00

CPC分类号： H04L1/0068 ,  H03M13/33 ,  H04L1/0046 ,  H04L1/0054

摘要： A synchronization method in Viterbi decoder is disclosed. The synchronization method performs a fast and an effective synchronization by depuncturing and Viterbi-decoding transmitted convolutional codes punctured in a predetermined puncturing pattern assuming that a code rate is 5/6, comparing the calculated CBER to a high/low threshold value, determining a code rate group to which the code rate of the convolutional codes belong, and performing a code rate detecting process, a phase synchronization and a pattern synchronization. Therefore, when performing the Viterbi decoding, a fast and more effective synchronization can be performed with improved efficiency.

摘要翻译： 公开了维特比解码器中的同步方法。 所述同步方法通过解码穿孔进行快速和有效的同步，并且以假定代码率为5/6的方式，以预定的打孔图案打孔的已发送卷积码进行维特比解码，将所计算的CBER与高/低阈值进行比较， 卷积码的码率所属的速率组，执行码率检测处理，相位同步和模式同步。 因此，当进行维特比解码时，能够以提高的效率进行快速且更有效的同步。

公开(公告)号：US5878092A

公开(公告)日：1999-03-02

申请号：US876554

申请日：1997-06-16

申请人： Young-Bae Choi

发明人： Young-Bae Choi

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/23 ,  H03M13/41 ,  H03M13/12

CPC分类号： H03M13/6502 ,  H03M13/4169

摘要： A trace-back apparatus to select a most likely path for use in a Viterbi decoder comprises one or more processing elements to carry out tracing-back based on a sequence of decision vectors coupled among themselves in a pipeline fashion. In each processing element, N number of decision vectors are delayed during a predetermined period to generate 1-step to N-step delayed decision vectors; and an input state is stored during the predetermined period to generate an 1-step delayed state; and multiplexing means multiplexs sequentially the 1-step to N-step delayed decision vectors based on the 1-step delayed state to provide an N-step trace-back state to the next processing element.

摘要翻译： 选择在维特比解码器中使用的最可能路径的追溯装置包括一个或多个处理元件，用于基于以它们之间的流水线方式耦合在一起的决定向量序列来执行追溯。 在每个处理单元中，N个判决向量在预定的周期内被延迟，以产生1步到N阶延迟判决向量; 并且在预定周期期间存储输入状态以产生一步延迟状态; 并且多路复用装置基于1级延迟状态将1级顺序复用到N级延迟判决向量，以向下一个处理元件提供N级跟踪状态。

公开(公告)号：US20100172196A1

公开(公告)日：2010-07-08

申请号：US12727185

申请日：2010-03-18

申请人： Kwang Jin Na ,  Young Bae Choi

发明人： Kwang Jin Na ,  Young Bae Choi

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input period by using an internal clock signal according to CAS latency under a read command, and generating the data strobe signal by using the pulses, and which can improve reliability of the circuit operation by precisely controlling operation timing with the internal clock signal.

摘要翻译： 本发明公开了一种用于在DDR存储器件中产生数据选通信号的电路及其方法，该电路可以通过仅在数据选通信号输入中产生用于产生数据选通信号的脉冲来精确地区分数据选通信号的前同步码和后同步周期 通过在读取命令下使用根据CAS等待时间的内部时钟信号，并且通过使用脉冲产生数据选通信号，并且通过利用内部时钟信号精确控制操作定时，可以提高电路操作的可靠性。

公开(公告)号：US20050105376A1

公开(公告)日：2005-05-19

申请号：US10874326

申请日：2004-06-24

申请人： Young-Bae Choi

发明人： Young-Bae Choi

IPC分类号： G11C11/40 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C7/1051 ,  G11C7/103 ,  G11C7/106 ,  G11C7/1066

摘要： A data output control circuit for use in a synchronous semiconductor memory device, which has a plurality of CAS latency modes, includes a signal generating unit for generating an internal signal corresponding to an input command; a CAS latency mode control unit for outputting the internal signal as a controlled internal signal; a signal shifting unit for generating a plurality of shifted signals by synchronizing the controlled internal signal with a DLL clock signal; and a data output enable signal generating unit for outputting one of the plurality of shifted signals as a data output enable signal depending on a plurality of control signals, wherein each of the plurality of control signals corresponds to two or more continuous CAS latency modes.

摘要翻译： 一种用于具有多个CAS等待时间模式的同步半导体存储器件中的数据输出控制电路，包括用于产生对应于输入命令的内部信号的信号产生单元; CAS延迟模式控制单元，用于输出内部信号作为受控的内部信号; 信号移位单元，用于通过使受控内部信号与DLL时钟信号同步来产生多个移位信号; 以及数据输出使能信号发生单元，用于根据多个控制信号输出多个移位信号中的一个作为数据输出使能信号，其中多个控制信号中的每一个对应于两个或更多个连续的CAS等待时间模式。

公开(公告)号：US06525581B1

公开(公告)日：2003-02-25

申请号：US10033989

申请日：2001-12-28

申请人： Young Bae Choi

发明人： Young Bae Choi

IPC分类号： H03K3017

CPC分类号： H03K5/1565

摘要： The present invention discloses a duty correction circuit for and method of enabling a clock signal and a clock bar signal phase transited from the clock signal by a phase difference of 180° to obtain a duty of 50%. The duty correction circuit includes: a duty check block for determining the duty of a clock signal, and generating a control signal indicating a determination result; and a duty correction block for receiving the clock signal or a clock bar signal, having a phase difference of 180° from the clock signal, correcting the duty of one of the clock signal or the clock bar signal according to the control signal from the duty check block, and outputting the duty-corrected signal. The method includes several steps, which reflect the procedure for correction of the duty.

摘要翻译： 本发明公开了一种用于使时钟信号和时钟信号相位从时钟信号转换180°的相位差的占空比校正电路，以获得占空比为50％。 占空比校正电路包括：用于确定时钟信号的占空比的工作检查块，以及产生指示确定结果的控制信号; 以及用于接收与时钟信号相差180°的时钟信号或时钟条信号的占空比校正块，根据来自占空比的控制信号来校正时钟信号或时钟条信号之一的占空比 检查块，并输出占空比校正信号。 该方法包括几个步骤，反映了更正职责的程序。

公开(公告)号：US5928378A

公开(公告)日：1999-07-27

申请号：US916665

申请日：1997-08-22

申请人： Young-Bae Choi

发明人： Young-Bae Choi

IPC分类号： G06F11/10 ,  H03M7/00 ,  H03M13/23 ,  H03M13/39

CPC分类号： H03M13/39

摘要： An add/compare/select (ACS) processor in a Viterbi decoder is disclosed. The ACS processor comprises a plurality of processing elements for receiving two path metrics and two branch metrics, comparing each added values, and outputting two decision bits and two state metrics according to the compared result; a grouping unit for grouping N number of processing elements for corresponding N number of states into K number of units using the same state metrics and the same branch metrics; a multiplexer for multiplexing L (L=2K) number of path metrics provided from the grouping unit into two path metrics according to a predetermined clock signal, and outputting them to a corresponding processing element; a first demultiplexer for receiving two decision bits outputted from the corresponding processing element, and demultiplexing them into L number of decision bits according to the clock signal; and a second demultiplexer for receiving two state metrics outputted from the corresponding processing element, and demultiplexing them into L number of state metrics according to the clock signal. Hence, the size of the hardware for ACS processor significantly decreases by having the above structure.

摘要翻译： 公开了维特比解码器中的加法/比较/选择（ACS）处理器。 ACS处理器包括用于接收两个路径量度和两个分支量度的多个处理元件，比较每个相加值，并根据比较结果输出两个判定位和两个状态度量; 分组单元，用于使用相同的状态度量和相同的分支度量将N个用于相应N个状态的处理元素分组为K个单位; 根据预定的时钟信号将从分组单元提供的L（L = 2K）个路径量度的L（2 = 2K）个复用器复用成两个路径度量，并将其输出到相应的处理单元; 第一解复用器，用于接收从相应处理单元输出的两个判定位，并根据时钟信号将它们解复用为L个判定位; 以及第二解复用器，用于接收从相应的处理元件输出的两个状态度量，并根据时钟信号将它们解复用为L个状态度量。 因此，通过具有上述结构，ACS处理器的硬件尺寸显着降低。