Invention Grant
- Patent Title: Method of manufacturing self aligned electrode with field insulation
- Patent Title (中): 制造具有场绝缘的自对准电极的方法
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Application No.: US10891038Application Date: 2004-07-15
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Publication No.: US06987065B2Publication Date: 2006-01-17
- Inventor: Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
- Applicant: Haruyuki Sorada , Takeshi Takagi , Akira Asai , Akira Inoue
- Applicant Address: JP Osaka
- Assignee: Matsushita Electric Industrial Co., Ltd.
- Current Assignee: Matsushita Electric Industrial Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2003-004471 20030110
- Main IPC: H01L21/311
- IPC: H01L21/311

Abstract:
The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.
Public/Granted literature
- US20040259319A1 Semiconductor device and process for manufacturing the same Public/Granted day:2004-12-23
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