发明授权
- 专利标题： Integrated circuit device having reduced substrate size and a method for manufacturing the same
- 专利标题（中）： 具有减小的基板尺寸的集成电路装置及其制造方法
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申请号： US10240651申请日： 2001-03-30
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公开(公告)号： US06989600B2公开(公告)日： 2006-01-24
- 发明人: Masaharu Kubo , Ichiro Anjo , Akira Nagai , Osamu Kubo , Hiromi Abe , Hitoshi Akamine
- 申请人： Masaharu Kubo , Ichiro Anjo , Akira Nagai , Osamu Kubo , Hiromi Abe , Hitoshi Akamine
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corporation
- 当前专利权人： Renesas Technology Corporation
- 当前专利权人地址： JP Tokyo
- 代理机构： Reed Smith LLP
- 代理商 Stanley P. Fisher, Esq.; Juan Carlos A. Marquez, Esq.
- 国际申请： PCT/JP01/02710 WO 20010330
- 国际公布： WO01/82367 WO 20011101
- 主分类号： H01L23/48
- IPC分类号： H01L23/48
摘要：
CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on a main surface of a glass substrate (30) different from the silicon substrate (1). The main surface of the silicon substrate (1) and the main surface of the glass substrate (30) are arranged in face-to-face relation with each other, and a plurality of microbumps (20A) formed at the uppermost portion of the silicon substrate (1) and a plurality of microbumps (20B) formed at the uppermost portion of the glass substrate (30) are electrically connected, thereby constituting the CMOS logic LSI as a whole.
公开/授权文献
- US20030148558A1 Integrated circuit and method of manufacturing thereof 公开/授权日：2003-08-07
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