公开(公告)号：US20090263943A1

公开(公告)日：2009-10-22

申请号：US12492276

申请日：2009-06-26

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/44

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

摘要翻译： 在MOSFET的栅电极，源极和漏极的表面上形成具有低电阻和小的漏电流的Co硅化物层，通过使用高纯度Co靶溅射沉积在晶片的主平面上的Co膜， Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

公开(公告)号：US07094655B2

公开(公告)日：2006-08-22

申请号：US11169585

申请日：2005-06-30

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

摘要翻译： 用于形成源区和漏区（S和D）的掺杂剂离子的注入步骤被划分为用于与阱区（3）形成ap / n结的掺杂剂离子的一次注入，并且一次注入掺杂剂离子 不影响源极和漏极区域（S和D）之间的p / n结的位置以及具有浅的注入深度和大的注入量的阱区域。 在对掺杂剂进行激活热处理之后，将源极/漏极区域的表面制成硅化钴12，使得源极/漏极区域（S和D）可以具有低电阻，并且ap / n结泄漏可以 减少

公开(公告)号：US06780757B2

公开(公告)日：2004-08-24

申请号：US10430402

申请日：2003-05-07

申请人： Masayuki Suzuki ,  Shinji Nishihara ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Sonoko Tohda ,  Hiroyuki Uchiyama ,  Hideaki Tsugane ,  Yoshiaki Yoshiura

发明人： Masayuki Suzuki ,  Shinji Nishihara ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Sonoko Tohda ,  Hiroyuki Uchiyama ,  Hideaki Tsugane ,  Yoshiaki Yoshiura

IPC分类号： H01L214763

CPC分类号： H01L21/76862 ,  H01L21/32051 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53223 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/04953 ,  H01L2924/00

摘要： A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：（a）在具有多个通孔的绝缘膜上沉积由氮化钛制成的第一底层膜; （b）在第一底层膜上沉积钨膜，并通过含氟等离子体将钨膜回蚀刻，从而将钨膜留在连接孔中; （c）溅射蚀刻第一底层膜的表面以从第一底层膜的表面除去氟; 和（d）在第一底层膜上形成铝膜。 还描述了通过该方法获得的半导体集成电路器件。

公开(公告)号：US06693001B2

公开(公告)日：2004-02-17

申请号：US09380735

申请日：2000-02-04

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L218238

CPC分类号： H01L21/28518 ,  H01L21/2855 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

摘要翻译： 通过使用高纯度Co靶通过溅射将沉积在晶片的主平面上的Co膜进行硅化，在MOSFET的栅极，源极和漏极的表面上形成具有低电阻和小的结漏电流的Co硅化物层 Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

公开(公告)号：US06670251B2

公开(公告)日：2003-12-30

申请号：US10005619

申请日：2001-12-07

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

公开(公告)号：US06545326B2

公开(公告)日：2003-04-08

申请号：US09910796

申请日：2001-07-24

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L31119

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/1083

摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

公开(公告)号：US06538329B2

公开(公告)日：2003-03-25

申请号：US09933163

申请日：2001-08-21

申请人： Masayuki Suzuki ,  Shinji Nishihara ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Sonoko Tohda ,  Hiroyuki Uchiyama ,  Hideaki Tsugane ,  Yoshiaki Yoshiura

发明人： Masayuki Suzuki ,  Shinji Nishihara ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Sonoko Tohda ,  Hiroyuki Uchiyama ,  Hideaki Tsugane ,  Yoshiaki Yoshiura

IPC分类号： H01L2348

CPC分类号： H01L21/76862 ,  H01L21/32051 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53223 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/04953 ,  H01L2924/00

摘要： A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.

公开(公告)号：US06503803B2

公开(公告)日：2003-01-07

申请号：US09766645

申请日：2001-01-23

申请人： Hiromi Todorobaru ,  Hideo Miura ,  Masayuki Suzuki ,  Shinji Nishihara ,  Shuji Ikeda ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Atushi Ogishima ,  Hiroyuki Uchiyama ,  Sonoko Abe

发明人： Hiromi Todorobaru ,  Hideo Miura ,  Masayuki Suzuki ,  Shinji Nishihara ,  Shuji Ikeda ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Atushi Ogishima ,  Hiroyuki Uchiyama ,  Sonoko Abe

IPC分类号： H01L21336

CPC分类号： H01L29/7845 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of fabricating a semiconductor device including forming an insulating film on a silicon substrate; forming a contact hole in the insulating film; depositing a titanium film to be in contact with the silicon substrate in the contact hole; and causing a heat reaction between the titanium film and the silicon substrate such that the titanium film is subjected to silicide reaction with the thickness 4 nm to 48 nm or, more preferably, with the thickness of 8 nm to 34 nm. In the instance where the contact hole is filled with doped polycrystal silicon material, the titanium film is deposited to be in contact with the polycrystal silicon in the contact hole. The silicon substrate/silicon body may have at least a MISFET formed thereon in which case the contact hole is formed to expose an active region of the MISFET, as one example.

摘要翻译： 公开了一种制造半导体器件的方法，包括在硅衬底上形成绝缘膜; 在绝缘膜上形成接触孔; 在接触孔中沉积与硅衬底接触的钛膜; 并且在钛膜和硅衬底之间引起热反应，使得钛膜以4nm至48nm的厚度进行硅化物反应，更优选地，以8nm至34nm的厚度进行硅化物反应。 在接触孔填充掺杂的多晶硅材料的情况下，沉积钛膜以与接触孔中的多晶硅接触。 作为一个示例，硅衬底/硅体可以具有至少形成在其上的MISFET，在这种情况下，形成接触孔以暴露MISFET的有源区。

公开(公告)号：US06268658B1

公开(公告)日：2001-07-31

申请号：US09500242

申请日：2000-02-08

申请人： Hiromi Todorobaru ,  Hideo Miura ,  Masayuki Suzuki ,  Shinji Nishihara ,  Shuji Ikeda ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Atushi Ogishima ,  Hiroyuki Uchiyama ,  Sonoko Abe

发明人： Hiromi Todorobaru ,  Hideo Miura ,  Masayuki Suzuki ,  Shinji Nishihara ,  Shuji Ikeda ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Atushi Ogishima ,  Hiroyuki Uchiyama ,  Sonoko Abe

IPC分类号： H01L2348

CPC分类号： H01L29/7845 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm or, preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.

摘要翻译： 半导体器件包括硅衬底，电布线金属，形成在硅衬底上的绝缘膜，形成在用于将硅衬底和电布线金属彼此连接的绝缘膜中的多个接触孔，以及硅化钛 膜在接触孔中形成。 硅化钛膜的厚度为10nm〜120nm，优选为20nm〜84nm。 半导体区域和电布线金属通过硅化钛膜彼此连接。

公开(公告)号：US08034715B2

公开(公告)日：2011-10-11

申请号：US12492276

申请日：2009-06-26

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/44 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

摘要翻译： 在MOSFET的栅电极，源极和漏极的表面上形成具有低电阻和小的漏电流的Co硅化物层，通过使用高纯度Co靶溅射沉积在晶片的主平面上的Co膜， Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。