发明授权
- 专利标题: Method and apparatus for multiple row caches per bank
- 专利标题(中): 每行多行缓存的方法和装置
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申请号: US10749690申请日: 2003-12-30
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公开(公告)号: US06990036B2公开(公告)日: 2006-01-24
- 发明人: John B. Halbert , Robert M. Ellis , Kuljit S. Bains , Chris B. Freeman
- 申请人: John B. Halbert , Robert M. Ellis , Kuljit S. Bains , Chris B. Freeman
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G11C7/00
- IPC分类号: G11C7/00
摘要:
Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.
公开/授权文献
- US20050146974A1 Method and apparatus for multiple row caches per bank 公开/授权日:2005-07-07
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