公开(公告)号：US09536863B2

公开(公告)日：2017-01-03

申请号：US13994919

申请日：2011-12-22

申请人： Todd A. Hinck ,  Zuoguo Wu ,  Aaron Martin ,  Andrew W. Martwick ,  John B. Halbert

发明人： Todd A. Hinck ,  Zuoguo Wu ,  Aaron Martin ,  Andrew W. Martwick ,  John B. Halbert

IPC分类号： G06F13/12 ,  G06F13/38 ,  H01L25/065 ,  H04B1/40 ,  H01L23/538 ,  H01L23/48 ,  H01L23/66 ,  H01L25/11

CPC分类号： H01L25/0655 ,  G06F13/385 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/66 ,  H01L25/115 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H04B1/40 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2224/0401

摘要： Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

摘要翻译： 用于互连集成电路管芯的装置。 第一组单端发射机电路包括在第一裸片上。 发射机电路阻抗匹配，无均衡。 第一组单端接收器电路包括在第二管芯上。 接收器电路没有终端，没有均衡。 导电线耦合在第一组发射器电路和第一组接收器电路之间。 导线的长度相匹配。 第一芯片，第一组单端发射机电路，第二芯片，第一组单端接收器电路和导线布置在第一封装内。 第一组芯片包括第二组单端发射机电路。 发射机电路阻抗匹配，无均衡。 根据数据总线反转（DBI）方案发送从第二组发射机电路发送的数据。 第三组裸片包括第二组单端接收机电路。 接收器电路具有端接。 导电线耦合在第二组发射器电路和第二组接收器电路之间。 导线的长度匹配，第二组接收器电路设置在第二封装内。

公开(公告)号：US09530468B2

公开(公告)日：2016-12-27

申请号：US14498509

申请日：2014-09-26

申请人： John B. Halbert ,  Bruce A. Christenson ,  Kuljit S. Bains

发明人： John B. Halbert ,  Bruce A. Christenson ,  Kuljit S. Bains

IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  G06F13/16 ,  G06F21/79

CPC分类号： G11C7/1072 ,  G06F13/1668 ,  G06F13/1689 ,  G06F21/79 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  Y02D10/14

摘要： Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.

摘要翻译： 用于在存储器控制器和存储器件之间交换信息的技术和机制。 在一个实施例中，存储器控制器接收指示存储器设备访问该存储器设备的临时统一激活命令的阈值数量的信息。 由信息指示的阈值数小于待处理的合并激活命令的理论最大数量，基于存储器件的定时参数定义的理论最大数量。 在另一个实施例中，存储器控制器基于指示阈值数量的信息来限制合并的激活命令到存储器设备的通信。

公开(公告)号：US20140301152A1

公开(公告)日：2014-10-09

申请号：US13997959

申请日：2012-03-27

申请人： Christopher E. Cox ,  Kuljit Singh Bains ,  John B. Halbert

发明人： Christopher E. Cox ,  Kuljit Singh Bains ,  John B. Halbert

IPC分类号： G11C11/406

CPC分类号： G11C11/40615 ,  G11C7/00 ,  G11C7/08 ,  G11C11/40611 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/4065 ,  G11C2211/4068

摘要： Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

摘要翻译： 设备，系统和方法包括适应存储器件的读/写操作和自刷新模式的主动模式，以适应当读/写操作空闲时表示存储数据的电压电平的再充电。 至少一个寄存器源提供小于第一电压电平的第一电压电平和第二电压电平。 通过这样的配置，在活动模式期间，存储器件以由至少一个寄存器源提供的第一电压电平工作，并且在自刷新模式期间，存储器件以由第二电压电平 至少一个寄存器源。

公开(公告)号：US20140006703A1

公开(公告)日：2014-01-02

申请号：US13539415

申请日：2012-06-30

申请人： Kuljit S. Bains ,  John B. Halbert ,  Christopher P. Mozak ,  Theodore Z. Schoenborn ,  Zvika Greenfield

发明人： Kuljit S. Bains ,  John B. Halbert ,  Christopher P. Mozak ,  Theodore Z. Schoenborn ,  Zvika Greenfield

IPC分类号： G11C11/406

CPC分类号： G11C11/4091 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2212/7211 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622

摘要： A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

公开(公告)号：US20130313709A1

公开(公告)日：2013-11-28

申请号：US13994919

申请日：2011-12-22

申请人： Todd A. Hinck ,  Zuoguo Wu ,  Aaron Martin ,  Andrew W. Martwick ,  John B. Halbert

发明人： Todd A. Hinck ,  Zuoguo Wu ,  Aaron Martin ,  Andrew W. Martwick ,  John B. Halbert

IPC分类号： H01L25/065

CPC分类号： H01L25/0655 ,  G06F13/385 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/66 ,  H01L25/115 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H04B1/40 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2224/0401

摘要： Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

摘要翻译： 用于互连集成电路管芯的装置。 第一组单端发射机电路包括在第一裸片上。 发射机电路阻抗匹配，无均衡。 第一组单端接收器电路包括在第二管芯上。 接收器电路没有终端，没有均衡。 导电线耦合在第一组发射器电路和第一组接收器电路之间。 导线的长度相匹配。 第一芯片，第一组单端发射机电路，第二芯片，第一组单端接收器电路和导线布置在第一封装内。 第一组芯片包括第二组单端发射机电路。 发射机电路阻抗匹配，无均衡。 根据数据总线反转（DBI）方案发送从第二组发射机电路发送的数据。 第三组裸片包括第二组单端接收机电路。 接收器电路具有端接。 导电线耦合在第二组发射器电路和第二组接收器电路之间。 导线的长度匹配，第二组接收器电路设置在第二封装内。

公开(公告)号：US08130576B2

公开(公告)日：2012-03-06

申请号：US12165214

申请日：2008-06-30

申请人： Kuljit S. Bains ,  John B. Halbert

发明人： Kuljit S. Bains ,  John B. Halbert

IPC分类号： G11C7/00

CPC分类号： G06F13/161 ,  Y02D10/14

摘要： Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了用于提高存储器设备中的吞吐量的方法和装置。 在一个实施例中，通过预充电管理的细粒度来增加存储器吞吐量。 在一个实施例中，可以使用三个单独的预充电定时，例如每个存储体组和/或每个存储器件优化每个存储体。 还公开并要求保护其他实施例。

公开(公告)号：US07050351B2

公开(公告)日：2006-05-23

申请号：US10750038

申请日：2003-12-30

申请人： John B. Halbert ,  Robert M. Ellis ,  Kuljit S. Bains ,  Chris B. Freeman

发明人： John B. Halbert ,  Robert M. Ellis ,  Kuljit S. Bains ,  Chris B. Freeman

IPC分类号： G11C8/00

CPC分类号： G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C11/4096 ,  G11C2207/005

摘要： Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.

摘要翻译： 提供和使用隔离器组，以使得能够通过与子阵列相关联的一行读出放大器将存储器件组的子阵列内的至少一行存储器单元的内容缓存以使得能够更快地访问内容读取内容 通过读取操作使至少一行直接从存储器单元行读取数据从读出放大器行读取。

公开(公告)号：US06820163B1

公开(公告)日：2004-11-16

申请号：US09666489

申请日：2000-09-18

申请人： James A. McCall ,  Randy M. Bonella ,  John B. Halbert ,  Jim M. Dodd ,  Chung Lam

发明人： James A. McCall ,  Randy M. Bonella ,  John B. Halbert ,  Jim M. Dodd ,  Chung Lam

IPC分类号： G06F1300

CPC分类号： G11C7/1006 ,  G06F13/4256

摘要： Buffering data transfer between a chipset and memory modules is disclosed. The disclosure includes providing and configuring at least one buffer. The buffers are provided in an interface between a chipset and memory modules. The buffers allow the interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the at least one buffer. The second sub-interface is between the at least one buffer and the memory modules. The buffers are then configured to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

摘要翻译： 公开了在芯片组和存储器模块之间缓冲数据传输。 本公开包括提供和配置至少一个缓冲器。 缓冲器提供在芯片组和存储器模块之间的接口中。 缓冲区允许将接口拆分为第一和第二子接口。 第一子接口在芯片组和至少一个缓冲器之间。 第二子接口位于至少一个缓冲器和存储器模块之间。 然后将缓冲器配置为适当地锁存正在芯片组和存储器模块之间传输的数据。 第一子接口和第二子接口彼此独立地操作，但是彼此同步。

公开(公告)号：US06742098B1

公开(公告)日：2004-05-25

申请号：US09678751

申请日：2000-10-03

申请人： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

发明人： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC分类号： G06F1200

CPC分类号： G06F13/4256

摘要： Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

摘要翻译： 公开了使用新的存储器模块结构的存储器系统的方法和装置。 在一个实施例中，存储器模块具有两个等级的存储器件，每个等级连接到两个64位宽数据寄存器中对应的一个。 数据寄存器连接到120：64多路复用器/解复用器的两个64位宽端口，64位宽数据缓冲器连接到多路复用器/解复用器的相对端口。 控制器同步数据寄存器，多路复用器/解复用器和数据缓冲器的操作。 在操作环境中，数据缓冲器连接到存储器总线。 当执行数据访问时，在单个数据访问期间，两者都与其对应的数据寄存器交换数据信令。 在缓冲器中，存储器总线数据传输发生在两个连续的时钟周期中，每个等级都有一个周期。 这允许存储器总线传输速率对于相同的存储器总线宽度和存储器件速度来说是双倍的。

公开(公告)号：US06487102B1

公开(公告)日：2002-11-26

申请号：US09666528

申请日：2000-09-18

申请人： John B. Halbert ,  Randy M. Bonella

发明人： John B. Halbert ,  Randy M. Bonella

IPC分类号： G11C502

CPC分类号： G11C8/12 ,  G11C5/02 ,  G11C5/04

摘要： The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.

摘要翻译： 本发明利用缓冲器来隔离存储器件堆叠，从而利用可堆叠的存储器件可用的增加的存储器密度，同时降低容性负载。 根据本发明的存储器模块可以包括堆叠的存储器件和缓冲器，其耦合到第一和第二存储器件并被布置成将第一和第二存储器件与总线电容隔离。 在根据本发明的存储器系统中，存储器件的多个缓冲堆栈优选地以点对点布置耦合，从而进一步减小电容负载。