- 专利标题: Electronic device manufacturing method
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申请号: US10835319申请日: 2004-04-30
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公开(公告)号: US06998342B2公开(公告)日: 2006-02-14
- 发明人: Tetsuo Matsuda , Hiroshi Toyoda , Hisashi Kaneko
- 申请人: Tetsuo Matsuda , Hiroshi Toyoda , Hisashi Kaneko
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Finnegan, Henderson, Farabow, Garrett, & Dunner, L.L.P.
- 优先权: JP2000-336194 20001102
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.
公开/授权文献
- US20040203221A1 Electronic device manufacturing method 公开/授权日:2004-10-14
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