公开(公告)号：US20100258854A1

公开(公告)日：2010-10-14

申请号：US12821708

申请日：2010-06-23

Applicant: Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

Inventor： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

IPC: H01L27/088

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Abstract translation: 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

公开(公告)号：US07214305B2

公开(公告)日：2007-05-08

申请号：US10636614

申请日：2003-08-08

Applicant: Tetsuo Matsuda ,  Hisashi Kaneko

Inventor： Tetsuo Matsuda ,  Hisashi Kaneko

IPC: C25D5/02 ,  C23C28/00

CPC classification number: H01L21/76879 ,  C25D5/02 ,  C25D5/022 ,  C25D5/34 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76873 ,  H05K3/107 ,  H05K3/423 ,  H05K2203/0392

Abstract: Disclosed is a method of manufacturing an electronic device, comprising forming a concave portion on the surface of a base member, forming an electrically conductive seed layer on that surface of the base member on which a plated film is to be formed, and applying an electrolytic plating treatment with the seed layer used as a common electrode under the condition that a substance for accelerating the electrolytic plating is allowed to be present in the concave portion of the base member in an amount larger than that on the surface of the base member to form a plated film.

Abstract translation: 公开了一种电子设备的制造方法，其特征在于，在基材的表面形成凹部，在要形成镀膜的基材的表面上形成导电种子层， 使用作为公共电极的种子层进行电镀处理，条件是允许电解电镀用的物质以比基材的表面上的量大的量存在于基材的凹部中以形成 镀膜。

公开(公告)号：US20050211560A1

公开(公告)日：2005-09-29

申请号：US11135328

申请日：2005-05-24

Applicant: Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

Inventor： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

IPC: C25D7/12 ,  C25D5/02 ,  C25D5/06 ,  C25D5/16 ,  C25D17/00 ,  C25D17/06 ,  C25D17/12 ,  H01K3/10 ,  H01L21/288 ,  H01L21/768 ,  H05K3/42

CPC classification number: C25D5/16 ,  C25D5/02 ,  C25D5/06 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

Abstract translation: 对形成在具有凹陷图案的基板上的导电层施加阴极电位。 将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。 此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。 由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。 因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。

公开(公告)号：US06913681B2

公开(公告)日：2005-07-05

申请号：US10107425

申请日：2002-03-28

Applicant: Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

Inventor： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

IPC: C25D7/12 ,  C25D5/02 ,  C25D5/06 ,  C25D5/16 ,  C25D17/00 ,  C25D17/06 ,  C25D17/12 ,  H01K3/10 ,  H01L21/288 ,  H01L21/768 ,  H05K3/42 ,  C25D5/00 ,  C25D5/22 ,  C25D21/12

CPC classification number: C25D5/16 ,  C25D5/02 ,  C25D5/06 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

Abstract translation: 对形成在具有凹陷图案的基板上的导电层施加阴极电位。 将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。 此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。 由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。 因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。

公开(公告)号：US06767437B2

公开(公告)日：2004-07-27

申请号：US09860514

申请日：2001-05-21

Applicant: Tetsuo Matsuda ,  Hisashi Kaneko ,  Koji Mishima ,  Natsuki Makino ,  Junji Kunisawa

Inventor： Tetsuo Matsuda ,  Hisashi Kaneko ,  Koji Mishima ,  Natsuki Makino ,  Junji Kunisawa

IPC: C25D1700

CPC classification number: C25D17/001 ,  Y10S204/07

Abstract: In an electroplating apparatus, an electrolytic agent is filled into the portion between an anode and a dummy cathode which is opposite substantially face to face and parallel to the anode, and an electric current is supplied to this portion, thereby suppressing changes in properties of a black film during the period in which plating to a substrate to be processed is stopped. In particular, by applying an electric current to the anode immediately before plating to the substrate is resumed, the film formation characteristics of plating to the substrate can be maximally stabilized. This can reduce the consumption power and dissolution of the anode. This apparatus is particularly effective in copper plating in which the formation of a black film is significant.

Abstract translation: 在电镀装置中，电解质被填充到阳极和虚拟阴极之间的与阳极基本上面对并且平行的方向相反的部分中，并且向该部分提供电流，从而抑制了 在停止对待处理的基板的电镀期间的黑色膜。 特别地，通过在电镀到基板之前立即向阳极施加电流，电镀到基板的成膜特性可以最大程度地稳定。 这可以降低阳极的消耗功率和溶解度。 该装置在形成黑色膜的铜电镀中特别有效。

公开(公告)号：US06764585B2

公开(公告)日：2004-07-20

申请号：US09985051

申请日：2001-11-01

Applicant: Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

Inventor： Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

IPC: B05D512

CPC classification number: H01L21/76874 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/405 ,  C23C18/54 ,  C23C28/00 ,  C25D7/123 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

Abstract translation: 一种电子器件制造方法，包括在基板上形成绝缘膜，形成包含所述绝缘膜中的互连槽和孔中的至少一个的待填充区域，形成含有催化剂金属的第一导电膜，其加速 化学镀，以便将要填充区域的内表面排列，通过化学镀在第一导电膜上形成第二导电膜，以便将被填充区域的内表面经由 第一导电膜，并且通过电镀在第二导电膜上形成第三导电膜，以便经由第一导电膜和第二导电膜填充待填充区域。

公开(公告)号：US06746589B2

公开(公告)日：2004-06-08

申请号：US09955115

申请日：2001-09-19

Applicant: Koji Mishima ,  Hiroaki Inoue ,  Natsuki Makino ,  Junji Kunisawa ,  Kenji Nakamura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Toshiyuki Morita

Inventor： Koji Mishima ,  Hiroaki Inoue ,  Natsuki Makino ,  Junji Kunisawa ,  Kenji Nakamura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Toshiyuki Morita

IPC: C25D500

CPC classification number: H01L21/2885 ,  C25D5/04 ,  C25D5/08 ,  C25D21/12 ,  H01L21/7684 ,  H01L21/76877

Abstract: The present invention relates to a plating method and a plating apparatus which can attain embedding of copper into fine interconnection patterns with use of a plating liquid having high throwing power and leveling properties, and which can make film thickness of a plated film substantially equal between an interconnection region and a non-interconnection region. A plating method comprises filling a plating liquid containing metal ions and an additive into a plating space formed between a substrate and an anode disposed closely to the substrate so as to face the substrate, and changing concentration of the additive in the plating liquid filled into the plating space during a plating process.

公开(公告)号：US06638411B1

公开(公告)日：2003-10-28

申请号：US09492138

申请日：2000-01-27

Applicant: Koji Mishima ,  Mizuki Nagai ,  Ryoichi Kimizuka ,  Tetsuo Matsuda ,  Hisashi Kaneko

Inventor： Koji Mishima ,  Mizuki Nagai ,  Ryoichi Kimizuka ,  Tetsuo Matsuda ,  Hisashi Kaneko

IPC: C25D534

CPC classification number: C25D17/001 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H05K3/22 ,  H05K2203/0392 ,  H05K2203/122 ,  Y10S205/917

Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.

Abstract translation: 本发明涉及一种使用例如硫酸铜溶液在铜的电镀上分离金属铜的方法和装置，以在基板的表面上产生铜互连。 使基板与包含在电镀液中的含有有机物质和硫化合物的至少一种的处理液接触至少一次。 此后，使基板与电镀液接触以对基板进行平板化。

公开(公告)号：US06403997B1

公开(公告)日：2002-06-11

申请号：US09621450

申请日：2000-07-21

Applicant: Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

Inventor： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

IPC: H01L2976

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底的围绕着具有第一侧壁绝缘膜的伪栅极图案的部分上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。

公开(公告)号：US06375823B1

公开(公告)日：2002-04-23

申请号：US09500645

申请日：2000-02-09

Applicant: Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

Inventor： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

IPC: C25D506

CPC classification number: C25D5/16 ,  C25D5/02 ,  C25D5/06 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

Abstract translation: 对形成在具有凹陷图案的基板上的导电层施加阴极电位。 将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。 此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。 由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。 因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。