- 专利标题: Semiconductor integrated circuit and a method of testing the same
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申请号: US10083399申请日: 2002-02-27
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公开(公告)号: US07000160B2公开(公告)日: 2006-02-14
- 发明人: Toshihiro Tanaka , Yutaka Shinagawa , Masahiko Kimura , Isao Nakamura
- 申请人: Toshihiro Tanaka , Yutaka Shinagawa , Masahiko Kimura , Isao Nakamura
- 申请人地址: JP Tokyo JP Tokyo
- 专利权人: Renesas Technology Corp.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人: Renesas Technology Corp.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人地址: JP Tokyo JP Tokyo
- 代理机构: Miles & Stockbridge P.C.
- 优先权: JP2001-125275 20010424
- 主分类号: G01R31/28
- IPC分类号: G01R31/28
摘要:
A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.