Invention Grant
- Patent Title: Semiconductor device having elevated source/drain
- Patent Title (中): 具有升高的源极/漏极的半导体器件
-
Application No.: US10206809Application Date: 2002-07-26
-
Publication No.: US07002223B2Publication Date: 2006-02-21
- Inventor: Hyung-Shin Kwon
- Applicant: Hyung-Shin Kwon
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Marger Johnson & McCollom, P.C.
- Priority: KR2001-45397 20010727; KR2002-33981 20020618
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119

Abstract:
The present invention provides a semiconductor device having an elevated source/drain and a method of fabricating the same. In the semiconductor device, an active region is defined at a predetermined region of a semiconductor substrate and a gate electrode is formed to cross over the active region. First and second insulating layer patterns are sequentially stacked on sidewalls of the gate electrode, and a silicon epitaxial layer adjacent to edges of the first and second insulating layer patterns is formed on the active region. The edge of the first insulating layer pattern is protruded from the edge of the second insulating layer pattern to be covered with the silicon epitaxial layer whose predetermined region is silicided. Further, the method includes defining an active region a semiconductor substrate, forming a gate electrode crossing over the active region, sequentially stacking first and second insulating layer patterns an active region adjacent to opposite sides of the gate electrode, forming a silicon epitaxial layer on the active region to be adjacent to edges of the first and second insulating layer patterns, and siliciding at least a part of the silicon epitaxial layer. The edge of the first insulating layer pattern contacting the active region is protruded from the edge of the second insulating layer pattern, and the silicon epitaxial layer covers the protruded edge of the first insulating layer pattern.
Public/Granted literature
- US20030025163A1 Semiconductor device having elevated source/drain and method of fabricating the same Public/Granted day:2003-02-06
Information query
IPC分类: