发明授权
US07005708B2 Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling
有权
最小尺寸,全硅化MOS驱动器和ESD保护设计,实现优化的手指间耦合
- 专利标题: Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling
- 专利标题(中): 最小尺寸,全硅化MOS驱动器和ESD保护设计,实现优化的手指间耦合
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申请号: US10435817申请日: 2003-05-12
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公开(公告)号: US07005708B2公开(公告)日: 2006-02-28
- 发明人: Markus Paul Josef Mergens , Koen Gerard Maria Verhaege , Cornelius Christian Russ , John Armer , Phillip Czeslaw Jozwiak , Bart Keppens
- 申请人: Markus Paul Josef Mergens , Koen Gerard Maria Verhaege , Cornelius Christian Russ , John Armer , Phillip Czeslaw Jozwiak , Bart Keppens
- 申请人地址: US NJ Princeton BE Gistel
- 专利权人: Sarnoff Corporation,Sarnoff Europe
- 当前专利权人: Sarnoff Corporation,Sarnoff Europe
- 当前专利权人地址: US NJ Princeton BE Gistel
- 代理机构: William J. Burke, Esq.
- 主分类号: H01L23/62
- IPC分类号: H01L23/62
摘要:
An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.
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