发明授权
- 专利标题: High-K gate dielectric defect gettering using dopants
- 专利标题(中): 使用掺杂剂的高K栅介质缺陷吸杂
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申请号: US10335560申请日: 2002-12-31
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公开(公告)号: US07015088B2公开(公告)日: 2006-03-21
- 发明人: Luigi Colombo , James J. Chambers , Antonio Luis Pacheco Rotondaro
- 申请人: Luigi Colombo , James J. Chambers , Antonio Luis Pacheco Rotondaro
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Jacqueline J. Garner; W. James Brady, III; Frederick J. Telecky, Jr.
- 主分类号: H01L21/00
- IPC分类号: H01L21/00 ; H01L21/8242
摘要:
One or more aspects of the present invention relate to forming a transistor while passivating electrically active defects associated with a top portion of a layer of high-k dielectric material. The layer of high-k dielectric material is utilized to establish a high-k gate dielectric in the transistor. A gate electrode layer is formed over the layer of high-k dielectric material, and is patterned to form a gate structure that includes a gate electrode and the high-k gate dielectric. The electrically active defects are passivated utilizing materials containing dopants that are attracted to and neutralize the defects. The passivated defects thus do not interfere with other transistor doping processes (e.g., forming source and drain regions) and do not adversely affect resulting semiconductor device performance, reliability and yield.
公开/授权文献
- US20040127000A1 High-K gate dielectric defect gettering using dopants 公开/授权日:2004-07-01
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