发明授权
US07015723B2 Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation
失效
动态静态逻辑控制元件,用于发出控制信号结束与逻辑评估之间的间隔
- 专利标题: Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation
- 专利标题(中): 动态静态逻辑控制元件,用于发出控制信号结束与逻辑评估之间的间隔
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申请号: US10922271申请日: 2004-08-19
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公开(公告)号: US07015723B2公开(公告)日: 2006-03-21
- 发明人: Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
- 申请人: Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Weiss, Moy & Harris, P.C.
- 代理商 Andrew M. Harris; Casimer K. Salys
- 主分类号: H03K19/00
- IPC分类号: H03K19/00
摘要:
A dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation provides a compact circuit for blocking the indication of a non-evaluated state of a dynamic logic gate until a control signal has ended. The control signal is connected to a precharge input of the control element and a summing node is connected to one or more evaluation trees and to the control element output via an inverter. The inverter is connected to an override circuit that forces the output of the control element to a state opposite the precharge state until the control signal has ended. The output of the control element then assumes a state corresponding to the precharge state until an evaluation occurs. The control element output thus produces a window signal indicating the interval between the end of the control signal and the evaluation.
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