- 专利标题: Method for testing semiconductor chips and semiconductor device
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申请号: US10159024申请日: 2002-06-03
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公开(公告)号: US07020817B2公开(公告)日: 2006-03-28
- 发明人: Yoshihide Komatsu
- 申请人: Yoshihide Komatsu
- 申请人地址: JP Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JP Osaka
- 代理机构: McDermott Will & Emery LLP
- 优先权: JP2001-169169 20010605
- 主分类号: G01R31/28
- IPC分类号: G01R31/28
摘要:
The delay characteristic of a chip under test on which a function test is performed first is detected by performing an edge search for stabilizing the test without awaiting the delay characteristic to be stabilized and the result of detection is stored in a memory. By using the delay characteristic stored in the memory, the function test is performed repeatedly on the chip under test till NG (FAIL) occurs. When NG occurs, the function test is performed repeatedly till the NG count of the chip under test reaches a first specified number. If the NG count exceeds the first specified number, the foregoing process is repeated starting from the edge search. If the NG count reaches a second specified number, the chip under test is determined to be defective and the test is ended.
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